ST72F321AR6T6 STMicroelectronics, ST72F321AR6T6 Datasheet - Page 120

• Manufacturer Part Number: ST72F321AR6T6
• Description: MCU 8BIT 32KB FLASH 64TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F321AR6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 5
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4842

ST72321Rx ST72321ARx ST72321Jx
I
Figure 66. Transfer Sequencing
Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
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10-bit Master transmitter
2
7-bit Slave receiver:
7-bit Slave transmitter:
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
10-bit Slave transmitter:
10-bit Master receiver:
S Address
S Address
S Header
S
S
S
C BUS INTERFACE (Cont’d)
EV5
EV5
EV5
Address
Address
Header
A
A
A
EV1
EV1 EV3
Address
A
A
A
Data1
EV6
EV6 EV8
EV9
A
Data1
S
Address
S
r
Data1
r
EV1
Header A
EV5
A
Data1
EV2
Data1
A
Header
A
A
Data2
EV3
EV7
EV6 EV8
A
EV1 EV3
A
Data2
EV8
A
Data2
EV2
EV6
A
Data2
Data1
Data1
EV2
A
.....
A
Data1
EV3
EV7
.....
DataN
A
A
A
EV8
EV8
A
EV3
DataN
.....
.....
EV7
A
....
DataN
.....
.....
.
DataN
EV2
DataN
.....
A
DataN
DataN
EV2
P
NA
NA
DataN
A
EV4
P
EV3-1
EV7
EV3-1
A
A
EV4
A
EV8
EV8
P
P
P
EV7
EV4
P
P
EV4
P