LH79520N0M000B1 Sharp Microelectronics, LH79520N0M000B1 Datasheet - Page 15

IC ARM7 BLUESTREAK MCU 176LQFP

LH79520N0M000B1

Manufacturer Part Number
LH79520N0M000B1
Description
IC ARM7 BLUESTREAK MCU 176LQFP
Manufacturer
Sharp Microelectronics
Series
BlueStreak ; LH7r
Datasheets

Specifications of LH79520N0M000B1

Rohs Status
RoHS non-compliant
Core Processor
ARM7
Core Size
32-Bit
Speed
77.4MHz
Connectivity
IrDA, Microwire, SPI, SSP, UART/USART
Peripherals
DMA, LCD, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LQFP
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
425-1820
LH79520N0M000

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LH79520N0M000B1
Manufacturer:
Sharp Microelectronics
Quantity:
10 000
System-on-Chip
SYSTEM DESCRIPTIONS
ARM720T Processor
cached core with an Advanced High-Performance Bus
(AHB) interface. The ARM720T features:
• 32-bit ARM7TDMI™ RISC Core
• 8KB Cache
• MMU (Windows CE enabled)
processors. For more information, see the ARM docu-
ment, ‘ARM720T (Rev 3) Technical Reference Manual’,
available on Sharp’s website at www.sharpsma.com.
ical Memory (PA) addresses to virtual memory
addresses. This allows physical memory, which is con-
Preliminary Data Sheet
The LH79520 microcontroller features the ARM720T
The processor is a member of the ARM7T family of
The LH79520 MMU provides a means to map Phys-
IMAGER
INTERFACE
MEMORY
Figure 3. LH79520 Application Diagram Example
CARD
FLASH/
SRAM/
SDRAM
DMA
CODEC
SSP
9/10/03
UART
strained by hardware to specific addresses, to be reor-
ganized at addresses identified by the user. These user
identified locations are called Virtual Addresses (VA).
When the MMU is enabled, Code and Data must be
built, loaded, and executed using Virtual Addresses
which the MMU translates to Physical Addresses. In
addition, the user may implement a memory protection
scheme by using the features of the MMU. Address
translation and memory protection services provided
by the MMU are controlled by the user. The MMU is
directly controlled through the System Control Copro-
cessor, Coprocessor 15 (CP15). The MMU is indirectly
controlled by a Translation Table (TT) and Page Tables
(PT) prepared by the user and established using a por-
tion of physical memory dedicated by the user to stor-
ing the TT and PT’s.
STN/
TFT/AD-TFT
LH79520
PWM
IR
PIO
SCREEN
CONTR.
TOUCH
UART
LH79520
79520-6A
15

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