ST10F269-DPR STMicroelectronics, ST10F269-DPR Datasheet - Page 154

• Manufacturer Part Number: ST10F269-DPR
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269-DPR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST10F269
Figure 78 : CLKOUT and READY
Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
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CLKOUT
ALE
RD, WR
Synchronous
READY
Asynchronous
READY
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling
point terminates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because
CLKOUT is not enabled), it must fulfill t
the command (see Note 4)).
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here.
For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC wait state this
delay is zero.
7. The next external bus cycle may start here.
t
t
58
32
3)
t
t
t
59
30
34
Running cycle 1)
37
in order to be safely synchronized. This is guaranteed, if READY is removed in response to
2)
t
t
33
31
t
t
35
58
3)
t
37
3)
t
t
36
59
t
5)
29
t
35
wait state
READY
3)
t
36
MUX / Tri-state 6)
t
60 4)
6)
7)