st10f269z1 STMicroelectronics, st10f269z1 Datasheet

st10f269z1

Manufacturer Part Number

st10f269z1

Description

St10f269 16-bit Mcu With Mac Unit, 256k Byte Flash Memory And 12k Byte Ram

Manufacturer

STMicroelectronics

Datasheet

1.ST10F269Z1.pdf (184 pages)

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Current page: 1 of 184
Download datasheet (4Mb)

■

September 2003

HIGH PERFORMANCE 32 OR 40 MHZ CPU WITH

DSP FUNCTION

– 16-bit CPU With 4-stage Pipeline

– 50ns (or 62.5ns) Instruction Cycle Time at 40MHz (or

– Multiply/accumulate Unit (Mac) 16 X 16-bit Multipli-

– Repeat Unit

– Enhanced Boolean Bit Manipulation Facilities

– Additional Instructions to Support HLL and Operat-

– Single-cycle Context Switching Support

MEMORY ORGANIZATION

– 128K or 256K Byte On-chip Flash Memory Single Volt-

– Up to 1K Erasing/programming Cycles

– Up to 16 MByte Linear Address Space For Code And

– 2K Byte On-chip Internal RAM (IRAM)

– 10K Byte On-chip Extension RAM (XRAM)

FAST AND FLEXIBLE BUS

– Programmable External Bus Characteristics for Dif-

– 8-bit or 16-bit External Data Bus

– Multiplexed or Demultiplexed External Address/data

– Five Programmable Chip-select Signals

– Hold-acknowledge Bus Arbitration Support

INTERRUPT

– 8-channel Peripheral Event Controller for Single Cy-

– 16-priority-level Interrupt System with 56 Sources,

TIMERS

– Two Multi-functional General Purpose Timer Units

TWO 16-CHANNEL CAPTURE / COMPARE UNITS

A/D CONVERTER

– 16-channel 10-bit

– 4.85µs Conversion Time at 40MHz CPU Clock

4-CHANNEL PWM UNIT

SERIAL CHANNELS

– Synchronous / Asynchronous Serial Channel

– High-speed Synchronous Channel

32MHz) Max CPU Clock

cation, 40-bit Accumulator

ing Systems

age With Erase/program Controller

Data (5 MBytes With CAN)

ferent Address Ranges

Buses

cle Interrupt Driven Data Transfer

Sampling Rate Down to 25ns at 40MHz (31.25ns at

32MHz)

with 5 Timers

(6.06µs at 32MHz)

128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM

■

CAN1_RXD

CAN1_TXD

CAN2_RXD

CAN2_TXD

16-BIT MCU WITH MAC UNIT,

PQFP144 (28 x 28 mm) (Plastic Quad Flat Pack)

TQFP144 (20 x 20 x 1.40 mm) (Thin Quad Flat Pack)

TWO CAN 2.0B INTERFACES OPERATING ON

ONE OR TWO CAN BUSSES (30 OR 2x15

MESSAGE OBJECTS)

FAIL-SAFE PROTECTION

– Programmable Watchdog Timer

– Oscillator Watchdog

ON-CHIP BOOTSTRAP LOADER

CLOCK GENERATION

– On-chip PLL

– Direct or Prescaled Clock Input

REAL TIME CLOCK

UP TO 111 GENERAL PURPOSE I/O LINES

– Individually Programmable as Input, Output or Spe-

– Programmable Threshold (Hysteresis)

IDLE AND POWER DOWN MODES

SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED

REGULATOR FOR 2.7 or 3.3 V CORE SUPPLY).

TEMPERATURE RANGES: -40 +125

144-PIN PQFP/TQFP PACKAGES

cial Function

128K or 256KByte

10K Byte

Flash Memory

XRAM

CAN1

CAN2

Port 6

Por t 5

CPU-Core and MAC Unit

ST10F269Zx

BRG

Port 3

Interrupt Controller

BRG

PEC

Port 7

DATASHEET

-40 to 85°C

3.3V

XTAL1

Port 8

Watchdog

Oscillator

and PLL

2K Byte

Internal

Regulator

RAM

Voltage

1/184

XTAL2

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