st10f269z1 STMicroelectronics, st10f269z1 Datasheet - Page 133
st10f269z1
Manufacturer Part Number
st10f269z1
Description
St10f269 16-bit Mcu With Mac Unit, 256k Byte Flash Memory And 12k Byte Ram
Manufacturer
STMicroelectronics
Datasheet
1.ST10F269Z1.pdf
(184 pages)
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ST10F269
BUSCON0 (FF0Ch / 86h)
BUSCON1 (FF14h / 8Ah)
BUSCON2 (FF16h / 8Bh)
BUSCON3 (FF18h / 8Ch)
CLKEN
BYTDIS
ROMEN
SGTDIS
ROMS1
STKSZ
CSWEN0 CSREN0 RDYPOL0 RDYEN0
CSWEN1 CSREN1 RDYPOL1 RDYEN1
CSWEN2 CSREN2 RDYPOL2 RDYEN2
CSWEN3 CSREN3 RDYPOL3 RDYEN3
RW
RW
RW
RW
15
15
15
15
RW
RW
RW
RW
14
14
14
14
‘0’: Pins WR and BHE retain their normal function
‘1’: Pin WR acts as WRL, pin BHE acts as WRH.
System Clock Output Enable (CLKOUT)
‘0’: CLKOUT disabled: pin may be used for general purpose I/O
‘1’: CLKOUT enabled: pin outputs the system clock signal.
Disable/Enable Control for Pin BHE (Set according to data bus width)
‘0’: Pin BHE enabled
‘1’: Pin BHE disabled, pin may be used for general purpose I/O.
Internal Memory Enable (Set according to pin EA during reset)
‘0’: Internal Memory disabled: accesses to the Memory area use the external bus
‘1’: Internal Memory enabled.
Segmentation Disable/Enable Control
‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit)
‘1’: Segmentation disabled (Only IP is saved/restored).
Internal Memory Mapping
‘0’: Internal Memory area mapped to segment 0 (00’0000H...00’7FFFH)
‘1’: Internal Memory area mapped to segment 1 (01’0000H...01’7FFFH).
System Stack Size
Selects the size of the system stack (in the internal RAM) from 32 to 1024 words.
RW
RW
RW
RW
13
13
13
13
RW
RW
RW
RW
12
12
12
12
11
11
11
11
-
-
-
-
BUS ACT0 ALE CTL0
BUSACT1
BUSACT2
BUSACT3
RW
RW
RW
RW
10
10
10
10
20 - SPECIAL FUNCTION REGISTER OVERVIEW
2
SFR
SFR
SFR
SFR
ALECTL1
ALECTL2
ALECTL3
RW
RW
RW
RW
9
9
9
9
2
8
8
8
8
-
-
-
-
7
7
7
7
BTYP
BTYP
BTYP
BTYP
RW
RW
RW
RW
1
6
6
6
6
MTTC0 RWDC0
MTTC1 RWDC1
MTTC2 RWDC2
MTTC3 RWDC3
RW
RW
RW
RW
5
5
5
5
RW
RW
RW
RW
4
4
4
4
Reset Value: 0000h
Reset Value: 0000h
Reset Value: 0000h
Reset Value: 0xx0h
3
3
3
3
MCTC
MCTC
MCTC
MCTC
2
2
2
2
RW
RW
RW
RW
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1
1
1
1
0
0
0
0
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