ST10F269-DP STMicroelectronics, ST10F269-DP Datasheet
ST10F269-DP
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ST10F269-DP Summary of contents
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... This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice. ST10F269 PRELIMINARY DATA PQFP144 ( mm) (Plastic Quad Flat Pack) ORDER CODE: ST10F269-Q3 TWO CAN 2.0B INTERFACES OPERATING ON ONE OR TWO CAN BUSSES (30 OR 2x15 MESSAGE OBJECTS) FAIL-SAFE PROTECTION – ...
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... ST10F269 TABLE OF CONTENTS 1 - INTRODUCTION ........................................................................................................ 2 - PIN DATA ................................................................................................................... 3 - FUNCTIONAL DESCRIPTION ................................................................................... 4 - MEMORY ORGANIZATION ....................................................................................... 5 - INTERNAL FLASH MEMORY ................................................................................... 5.1 - OVERVIEW ................................................................................................................ 5.2 - OPERATIONAL OVERVIEW ...................................................................................... 5.3 - ARCHITECTURAL DESCRIPTION ............................................................................ 5.3.1 - Read Mode ................................................................................................................. 5.3.2 - Command Mode ......................................................................................................... 5.3.3 - Ready/Busy Signal ..................................................................................................... 5.3.4 - Flash Status Register ................................................................................................. 5.3.5 - Flash Protection Register ........................................................................................... 5.3.6 - Instructions Description .............................................................................................. ...
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... Alternate Functions of Port 3 ...................................................................................... 12.7 - PORT 4 ....................................................................................................................... 12.7.1 - Alternate Functions of Port 4 ...................................................................................... 12.8 - PORT 5 ....................................................................................................................... 12.8.1 - Alternate Functions of Port 5 ...................................................................................... 12.8.2 - Port 5 Schmitt Trigger Analog Inputs .......................................................................... 12.9 - PORT 6 ....................................................................................................................... 12.9.1 - Alternate Functions of Port 6 ...................................................................................... 12.10 - PORT 7 ....................................................................................................................... 12.10.1 - Alternate Functions of Port 7 ...................................................................................... 12.11 - PORT 8 ....................................................................................................................... 12.11.1 - Alternate Functions of Port 8 ...................................................................................... ST10F269 PAGE ...
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... ST10F269 TABLE OF CONTENTS 13 - A/D CONVERTER ...................................................................................................... 14 - SERIAL CHANNELS ................................................................................................. 14.1 - ASYNCHRONOUS / SYNCHRONOUS SERIAL INTERFACE (ASCO) .................... 14.1.1 - ASCO in Asynchronous Mode .................................................................................... 14.1.2 - ASCO in Synchronous Mode ...................................................................................... 14.2 - HIGH SPEED SYNCHRONOUS SERIAL CHANNEL (SSC) ..................................... 15 - CAN MODULES ......................................................................................................... 15.1 - CAN MODULES MEMORY MAPPING ...................................................................... 15.1.1 - CAN1 .................................................................................................................. ........ 15.1.2 - CAN2 .................................................................................................................. ........ ...
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... CLKOUT and READY ................................................................................................. 21.4.13 - External Bus Arbitration .............................................................................................. 21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing ........................................... 21.4.14.1 Master Mode................................................................................................................ 21.4.14.2 Slave mode.................................................................................................................. 22 - PACKAGE MECHANICAL DATA 23 - ORDERING INFORMATION ...................................................................................... ....................................................................................................... ........................................................................... ST10F269 PAGE 117 123 124 131 131 131 131 134 135 136 136 136 137 138 ...
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... I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL. ST10F269 is processed in 0.35 m CMOS technology. The MCU core and the logic is supplied with 3.3V on chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V ...
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... P7.0/POUT0 20 P7.1/POUT1 21 P7.2/POUT2 22 P7.3/POUT3 23 P7.4/CC28I0 24 P7.5/CC29I0 25 P7.6/CC30I0 26 P7.7/CC31I0 27 P5.0/AN0 28 P5.1/AN1 29 P5.2/AN2 30 P5.3/AN3 31 P5.4/AN4 32 P5.5/AN5 33 P5.6/AN6 34 P5.7/AN7 35 P5.8/AN8 36 P5.9/AN9 ST10F269-Q3 ST10F269 108 P0H.0/AD8 107 P0L.7/AD7 106 P0L.6/AD6 105 P0L.5/AD5 104 P0L.4/AD4 P0L.3/AD3 103 102 P0L.2AD2 101 P0L.A/AD1 100 P0L.0/AD0 ALE 97 READY 96 WR/WRL ...
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... ST10F269 Table 1 : Pin Description Symbol Pin Type P6 ... ... P8.0 - P8.7 9-16 I/O 9 I/O ... ... 16 I/O P7.0 - P7.7 19-26 I ... ... I/O ... ... 26 I/O P5.0 - P5.9 27-36 I P5.10 - P5.15 39- 8/160 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state ...
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... RxD0 ASC0 Data Input (Asynchronous) or I/O (Synchronous) P3.12 BHE External Memory High Byte Enable Signal WRH External Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Output / Slave Clock Input P3.15 CLKOUT System Clock Output (=CPU Clock) ST10F269 Function 9/160 ...
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... External Access Enable pin. A low level applied to this pin during and after Reset forces the ST10F269 to start the program from the external memory space. A high level forces the MCU to start in the internal memory space. ...
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... NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F269 to go into power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode. ...
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... ST10F269 Symbol Pin Type V 46, 72 82,93, 109, 126, 136, 144 V 18,45 55,71, 83,94, 110, 127, 139, 143 DC1 56 - DC2 17 - 12/160 Digital Supply Voltage during normal operation and idle mode. Digital Ground. 3.3V Decoupling pin: a decoupling capacitor of between this pin and nearest V ...
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... FUNCTIONAL DESCRIPTION The architecture of the ST10F269 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The Figure 3 : Block Diagram 256K Byte Flash Memory 10K Byte XRAM P4.5 CAN1_RXD CAN1 P4.6 CAN1_TXD P4.4 CAN2_RXD CAN2 P4.7 CAN2_TXD Port 6 8 block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F269 ...
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... Note Visibility of XBUS Peripherals is 00’C000h In order to keep the ST10F269 compatible with the ST10C167 and with the ST10F167, the XBUS peripherals can be selected to be visible and / or range 00’C000h accessible on the external address / data bus. CAN1EN and CAN2EN bits of XPERCON register register must be set ...
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... Figure 4 : ST10F269 On-chip Memory Mapping 14 05’0000 04’0000 10 0C 03’0000 02’0000 01’8000 05 04 01’0000 03 00’C000 02 00’6000 01 00’4000 00 00’0000 Data Absolute Page Memory Number Address * Bank 0L may be remapped from segment 0 to segment 1 (Bank 1L) by setting SYSCON-ROMS1 (before EINIT) Data Page Number and Absolute Memory Address are hexadecimal values ...
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... ST10F269 XPERCON (F024h / 12h CAN1EN CAN1 Enable Bit ‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if CAN2EN is also ‘0’. ...
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... CPU frequency up to 40MHz. Instruction fetches and data operand reads are performed with all addressing modes of the ST10F269 instruction set. In order to optimize the programming time of the internal Flash, blocks of 8K Bytes, 16K Bytes, 32K Bytes, 64K Bytes can be used. But the size of the blocks does not apply to the whole memory space, see details in Table 2 ...
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... ST10F269 Instructions and Commands All operations besides normal read operations are initiated and controlled by command sequences written to the Flash Command Interface (CI). The Command Interface (CI) interprets words written to the Flash memory and enables one of the following operations: – Read memory array – Program Word – ...
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... FSB.2, or Error on FSB.5 and Erase Timeout on FSB.3 bit. Any read attempt in Flash during EPC operation will automatically output these five bits. The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6 and FSB.7. Other bits are reserved for future use and should be masked. ST10F269 19/160 ...
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... ST10F269 Flash Status (see note for address FSB.7 Flash Status bit 7: Data Polling Bit Programming Operation: this bit outputs the complement of the bit 7 of the word being programmed, and after completion, will output the bit 7 of the word programmed. Erasing Operation: outputs a ‘0’ during erasing, and ‘1’ after erasing completion. ...
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... When this time-out period has elapsed, the erase starts. The status of the internal timer can be monitored through the level of FSB.3, if FSB.3 is ‘0’, the Block Erase command has been given and the timeout is running; if FSB.3 is ‘1’, the timeout has expired and the EPC is erasing the block(s). ST10F269 ...
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... ST10F269 If the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to Read Mode not necessary to program the block with 0000h as the EPC will do this automatically before the erasing to FFFFh. Read operations after the EPC has started, output the Flash Status Register ...
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... Note that Code Temporary Unprotection instruction must be used when it is necessary to modify the Flash with protected code (SCP), since the write/erase routines must be executed from a memory external to Flash space. Usually, the write/erase routines, executed in RAM, ends with a return to Flash space where a CTP instruction restore the protection. ST10F269 23/160 ...
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... ST10F269 Table 3 : Instructions Instruction Mne Cycle Read/Reset RD 1+ Read/Reset RD 3+ Program Word PW 4 Block Erase BE 6 Chip Erase CE 6 Erase Suspend ES 1 Erase Resume ER 1 Set Block/Code Protection SP 4 Read Protection RP 4 Status Block Temporary BTU 4 Unprotection Code Temporary CTU 1 Unprotection ...
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... Flash Memory Configuration The default memory configuration ST10F269 Memory is determined by the state of the EA pin at reset. This value is stored in the Internal ROM Enable bit (named ROMEN) of the SYSCON register. When ROMEN = 0, the internal Flash is disabled and external ROM is used for startup control. ...
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... ST10F269 5.5.2 - Basic Flash Access Control When accessing the Flash all command write addresses have to be located within the active Flash memory space. The active Flash memory space is that logical address range which is covered by the Flash after mapping. When using data page pointer (DPP) for addressing the Flash, make sure that address bit A15 and A14 of the command addresses are reflected in both LSBs of the selected data page pointer (A15 - DPPx ...
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... R6 with command address ;(used in command cycle 2) ;push data page pointer 0 and load it to point to ;segment 2 ;load register R7 with 1st CI enable command ;command cycle 1 ;load register R7 with 2cd CI enable command ;command cycle 2 ;load register R7 with Program Word command ;command cycle 3 ST10F269 27/160 ...
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... ST10F269 POP DPP0 EXTS R11, #1 MOV [R12], R13 Data_Polling: EXTS R11, #1 MOV R7, [R12] MOV R6, R7 XOR R7, R13 JNB R7.7, Prog_OK JNB R6.5, Data_Polling EXTS R11, #1 MOV R7, [R12] XOR R7, R13 JNB R7.7, Prog_OK Prog_Error: MOV R7, #0F0h EXTS R11, #1 MOV [R12], R7 ... ... ...
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... R7 with Read/Reset command ;use EXTended addressing for next MOV instruction ;address is don’t care for Read/Reset command ;here place specific Error handling code ;When erasing operation finished succesfully, ;Flash is set back automatically to normal Read Mode ST10F269 29/160 ...
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... Boot-ROM. No part of the standard mask Memory or Flash Memory area is required for this. After entering BSL mode and the respective initialization the ST10F269 scans the RXD0 line to receive a zero Byte, one start bit, eight ‘0’ data bits and one stop bit. ...
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... When the ST10F269 has entered BSL mode, the following configuration is automatically set (values that deviate from the normal reset values, are marked ): Disabled Watchdog Timer: Context Pointer CP: FA00h Stack Pointer SP: FA40h Register S0CON: 8011h Register S0BG: Acc. to ‘00’ Byte In this case, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited ...
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... BSL mode must be terminated first. The ST10F269 exits BSL mode upon a software reset that adds a (ignores the level on P0L. hardware reset (P0L.4 must be high). After a reset the ST10F269 will start executing from location 00’0000h of the the system internal Flash or the external memory, as programmed via pin EA. ...
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... The calculation of the serial Baud rate for ASC0 from the length of the first zero Byte that is received, allows the operation of the bootstrap loader of the ST10F269 with a wide range of Baud rates. However, the upper and lower limits have to be kept, in order to insure proper data transfer. ...
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... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F269’s instructions can be exe- cuted in one instruction cycle which requires 50ns at 40MHz CPU clock. For example, shift and rotate instructions are processed in one instruc- tion cycle independent of the number of bits to be shifted ...
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... The co-processor instructions extend the ST10 CPU instruction set with multiply, multiply-accu- mulate, 32-bit signed arithmetic operations. A new transfer instruction CoMOV has also been added to take benefit of the new addressing capa- bilities. ST10F269 Reset Value: 0xx0h ...
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... ST10F269 6.1.1 - Features 6.1.1.1 - Enhanced Addressing Capabilities – New addressing modes including a double indi- rect addressing mode with pointer post-modifi- cation. – Parallel Data Move : this mechanism allows one operand move during Multiply-Accumulate in- structions without penalty. – New tranfer instructions CoSTORE (for fast ac- cess to the MAC SFRs) and CoMOV (for fast memory to memory table transfer) ...
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... Instruction Set Summary The Table 4 lists the instructions of the ST10F269. The various addressing modes, instruction operation, parameters for conditional execution of instructions, opcodes and a detailed description of each instruc- tion can be found in the “ST10 Family Programming Manual”. Table 4 : Instruction Set Summary ...
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... ST10F269 Table 4 : Instruction Set Summary Mnemonic JNBS Jump relative and set bit if direct bit is not set CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met CALLS Call absolute subroutine in any code segment PCALL Push direct word register onto system stack and call absolute subroutine ...
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... CoMACRu CoMACRus CoMACRsu CoMACR, rnd CoMACRu, rnd CoMACRus, rnd CoMACRsu, rnd CoNOP CoNEG CoNEG, rnd CoRND CoSTORE CoMOV Addressing Modes [IDX ], [ [ [IDX ], [ [ [IDX ], [ [ [Rw m [IDX ] i [IDX ], [ CoReg n [Rw , Coreg n [IDX ], [ ST10F269 Repeatability Yes Yes Yes Yes Yes No No Yes Yes 39/160 ...
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... ST10F269 Mnemonic CoMACM CoMACMu CoMACMus CoMACMsu CoMACM- CoMACMu- CoMACMus- CoMACMsu- CoMACM, rnd CoMACMu, rnd CoMACMus, rnd CoMACMsu, rnd CoMACMR CoMACMRu CoMACMRus CoMACMRsu CoMACMR, rnd CoMACMRu, rnd CoMACMRus, rnd CoMACMRsu, rnd CoADD CoADD2 CoSUB CoSUB2 CoSUBR CoSUB2R CoMAX CoMIN CoLOAD CoLOAD- CoLOAD2 ...
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... QX ] (IDX ) (IDX ) - ( (Rwn) (Rwn) (Rwn) (Rwn (Rwn) (Rwn (Rwn) (Rwn (Rwn) (Rwn) - (QR j Description ST10F269 ]” refer to these addressing i Address Pointer Operation (no-op) (i=0,1) (i=0,1) ) (i, j =0, (i, j =0,1) j (no-op) (n=0-15) (n=0-15) ) (n=0-15; j =0, (n=0-15; j =0,1) j Address in Opcode 00000b 00001b 00010b ...
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... Programmable Chip Select Timing Control The ST10F269 allows the user to adjust the position of the CSx line changes. By default (after reset), the CSx lines change half a CPU clock cycle (12.5ns at 40MHz of CPU clock) after the rising edge of ALE. With the CSCFG bit set in the ...
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... Figure 11 : Chip Select Delay Normal Demultiplexed Segment (P4) Address (P1) ALE Normal CSx Unlatched CSx BUS (P0) RD BUS (P0) WR ALE Lengthen Demultiplexed Bus Cycle Data Data Read/Write Delay ST10F269 Bus Cycle Data Data Read/Write Delay 43/160 ...
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... When this counter reaches zero, a standard interrupt is performed corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F269 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. EXISEL (F1DAh / EDh ...
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... Interrupt Registers and Vectors Location List Table 7 shows all the available ST10F269 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 7 : Interrupt Sources Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 ...
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... ST10F269 Table 7 : Interrupt Sources (continued) Source of Interrupt or PEC Service Request CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ...
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... RESET RESET RESET NMI NMITRAP STKOF STOTRAP STKUF STUTRAP UNDOPC BTRAP PRTFLT BTRAP ILLOPA BTRAP ILLINA BTRAP ILLBUS BTRAP [002Ch - 003Ch] 0000h – 01FCh ST10F269 Reset Value 00h ILVL RW Vector Trap Location Number 00’0000h 00h 00’0000h 00h 00’0000h 00h 00’0008h 02h 00’ ...
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... ST10F269 9 - CAPTURE/COMPARE (CAPCOM) UNITS The ST10F269 has two 16 channels CAPCOM units as described in Figure 12. These support generation and control of timing sequences channels with a maximum resolution of 200ns at 40MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse ...
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... CPU clock are listed in the Table 10. The numbers for the timer periods are based on a reload value of 0000h. Note that some numbers may be rounded to 3 significant figures. TxIR TxIR , for the timer input Tx clocks. The timer input ST10F269 Interrupt Request Interrupt Request frequencies, 49/160 ...
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... ST10F269 Table 9 : Compare Modes Compare Modes Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set ‘ ...
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... Timer Input Selection T2I / T3I / T4I 001b 010b 011b 2.5MHz 1.25MHz 625kHz 400ns 0.8µs 1.6µs 26.2ms 52.4ms 104.8ms 100b 101b 110b 128 256 512 312.5kHz 156.25kHz 78.125kHz 3.2µs 6.4µs 12.8µs 209.7ms 419.4ms 838.9ms ST10F269 111b 1024 39.1kHz 25.6µs 1.678s 51/160 ...
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... ST10F269 Figure 15 : Block Diagram of GPT1 T2EUD CPU Clock n 2 n=3...10 T2IN CPU Clock n 2 n=3...10 T3IN T3EUD T4IN CPU Clock n 2 n=3...10 T4EUD 10.2 - GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both ...
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... T5EUD CPU Clock n 2 n=2...9 T5IN CAPIN T6IN CPU Clock n 2 n=2...9 T6EUD U/D T5 GPT2 Timer T5 Mode Control Clear Capture GPT2 CAPREL T6 GPT2 Timer T6 Mode Control U/D ST10F269 Interrupt Request Interrupt Request Reload Interrupt Request Toggle FF T60TL T6OUT to CAPCOM Timers 53/160 ...
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... ST10F269 11 - PWM MODULE The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and Figure 17 : Block Diagram of PWM Module Clock 1 Input Control Clock 2 Run * User readable / writeable register ...
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... PARALLEL PORTS 12.1 - Introduction The ST10F269 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. ST10F269 has 9 groups of I/O lines gathered as following: – Port time 8-bit port named P0L (Low as ...
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... ST10F269 Figure 18 : SFRs and Pins Associated with the Parallel Ports 56/160 ...
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... I/O’s Special Features 12.2.1 - Open Drain Mode Some of the I/O ports of ST10F269 support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired logical function. This feature is implemented for ports P2, P3, P4, ...
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... ST10F269 Figure 20 : Hysteresis for Special Input Thresholds Hysteresis Input level Bit state 12.2.3 - Output Driver Control The port output control registers POCONx allow to select the port output driver characteristics of a port. The aim of these selections is to adapt the output drivers to the application’s requirements, and to improve the EMI behaviour of the device ...
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... ESFR PN1DC RW Controlled Port Nibble 2 1 P0L.7...4 P0H.7...4 P1L.7...4 P1H.7...4 P2.11...8 P2.7...4 P3.11...8 P3.7...4 P4.7...4 P6.7...4 P7.7...4 P8.7...4 Reset Value: --00h PN1EC PN0DC RW RW ST10F269 0 P0L.3...0 P0H.3...0 P1L.3...0 P1H.3...0 P2.3...0 P3.3...0 P4.3...0 P6.3...0 P7.3...0 P8.3... PN0EC RW 59/160 ...
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... ST10F269 12.2.4 - Alternate Port Functions Each port line has one associated programmable alternate input or output function. – PORT0 and PORT1 may be used as address and data lines when accessing external memory. – Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of the CAP- COM units and/or with the outputs of the PWM module ...
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... RW RW SFR P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H ESFR DP0L.7 DP0L.6 DP0L.5 DP0L.4 DP0L.3 DP0L.2 DP0L.1 DP0L ESFR DP0H.7 DP0H.6 DP0H.5 DP0H.4 DP0H.3 DP0H.2 DP0H.1 DP0H ST10F269 Reset Value: --00h Reset Value: --00h Reset Value: --00h Reset Value: --00h ...
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... ST10F269 12.3.1 - Alternate Functions of PORT0 When an external bus is enabled, PORT0 is used as data bus or address/data bus. Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for I/O (provided that no other bus mode is enabled). PORT0 is also used to select the system start-up configuration ...
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... The Figure 22 shows the structure of a PORT0 pin. Alternate 1 Direction MUX 0 Alternate Function Enable Alternate Data Output 1 Port Data MUX Output 0 1 MUX 0 ST10F269 port output latch, otherwise P0H.y P0L.y Output Buffer Clock Input y = 7...0 Latch 63/160 ...
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... ST10F269 12.4 - PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halves of PORT1 can be written (via a PEC transfer) without effecting the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction registers DP1H and DP1L ...
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... The Figure 24 shows the structure of a PORT1 pin. 1 “1” MUX 0 Alternate Function Enable Alternate Data Output 1 Port Data MUX Output 0 Clock 1 MUX Input 0 Latch ST10F269 b) CC27IO CC26IO CC25IO CC24IO CAPCOM2 Capture Inputs only P1H.y P1L.y Output Buffer y = 7...0 65/160 ...
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... ST10F269 12.5 - Port 2 If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP2. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP2. ...
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... Fast External Interrupt 6 Input EX7IN Fast External Interrupt 7 Input a) CC15IO CC14IO CC13IO CC12IO CC11IO CC10IO CC9IO CC8IO CC7IO CC6IO CC5IO CC4IO CC3IO CC2IO CC1IO CC0IO CAPCOM1 Fast External Interrupt Input ST10F269 Alternate Function T7IN T7 External Count Input b) c) EX7IN T7IN EX6IN ...
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... ST10F269 The pins of Port 2 combine internal bus data with alternate data output before the port latch input. Figure 26 : Block Diagram of a Port 2 Pin Write ODP2.y Open Drain Latch Read ODP2.y Write DP2.y Direction Latch Read DP2.y 1 MUX Alternate 0 Data Output Write Port P2.y Compare Trigger Read P2 ...
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... SFR P3.8 P3.7 P3 SFR DP3 DP3 DP3 DP3 DP3 . ESFR ODP3 ODP3 ODP3 ODP3 ODP3 . ST10F269 Reset Value: 0000h P3.5 P3.4 P3.3 P3.2 P3 Reset Value: 0000h DP3 DP3 DP3 DP3 DP3 . Reset Value: 0000h ODP3 ODP3 ODP3 ODP3 ODP3 . ...
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... ST10F269 12.6.1 - Alternate Functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines, the two serial interfaces and the control lines BHE/WRH and CLKOUT. Table 16 : Port 3 Alternative Functions Port 3 Pin T0IN CAPCOM1 Timer 0 Count Input P3.0 P3 ...
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... Note: Enabling the CLKOUT function automati- cally enables the P3.15 output driver. Set- ting bit DP3.15=’1’ is not required. Alternate Data Output Port Data & Output 1 MUX 0 Alternate Data Input ST10F269 P3.y Output Buffer Clock Input Latch y = 13, 11...0 71/160 ...
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... ST10F269 Pin P3.12 (BHE/WRH) is another pin with an alternate output function, however, its structure is slightly different. After reset the BHE or WRH function must be used depending on the configuration. In either of these cases, there is no Figure 29 : Block Diagram of Pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) Write DP3.x ...
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... Note: Only bit 6 and 7 are implemented, all other bit will be read as “0”. SFR P4.7 P4 SFR DP4.7 DP4.6 DP4.5 DP4.4 DP4.3 DP4.2 DP4.1 DP4 ESFR ODP4.7 ODP4 ST10F269 Reset Value: --00h P4.5 P4.4 P4.3 P4.2 P4 Reset Value: --00h Reset Value: --00h ...
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... ST10F269 12.7.1 - Alternate Functions of Port 4 During external bus cycles that use segmentation (address space above 64K Bytes) a number of Port 4 pins may output the segment address lines. The number of pins that is used for segment address output determines the external address space which is directly accessible. The other pins of Port 4 may be used for general purpose I/O ...
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... Figure 31 : Block Diagram of a Port 4 Pin Write DP4.y Direction Latch Read DP4.y Write P4.y Port Output Latch Read P4.y 1 “1” MUX 0 Alternate Function Enable Alternate Data 1 Output MUX 0 1 MUX 0 ST10F269 P4.y Output Buffer Clock Input Latch y = 7...0 75/160 ...
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... ST10F269 Figure 32 : Block Diagram of P4.4 and P4.5 Pins Write DP4.x Direction Latch Read DP4.x Write P4.x Port Output Latch Read P4.x CANy.RxD XPERCON.a (CANyEN) XPERCON.b (CANzEN) 76/160 “1” 1 MUX 0 “0” 1 MUX Alternate Function 0 Enable Alternate Data 1 Output MUX 0 1 MUX 0 & ...
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... MUX 0 "0" 1 MUX Alternate Function 0 Enable Alternate 1 Data Output MUX 0 1 MUX 0 1 SFR P5.8 P5 MUX MUX 0 1 "1" MUX MUX 0 1 MUX MUX 0 Output Buffer Clock Input Latch (CAN Channel Reset Value: XXXXh P5.6 P5.5 P5.4 P5.3 P5 ST10F269 P4 P5.1 P5 77/160 ...
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... ST10F269 12.8.1 - Alternate Functions of Port 5 Each line of Port 5 is also connected to one of the multiplexer of the Analog/Digital Converter. All port lines (P5.15...P5.0) can accept analog signals (AN15...AN0 converted by the ADC. No special programming is required for pins that Table 18 : Port 5 Alternate Functions ...
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... P5DI DIS.10 DIS.9 DIS.8 DIS.7 DIS SFR P6.7 P6 SFR DP6.7 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6 ST10F269 Analog Switch P5.y/ANy y = 15...0 Reset Value: 0000h P5DI P5DI P5DI P5DI DIS.5 DIS.4 DIS.3 DIS.2 DIS Reset Value: --00h P6.5 P6.4 P6.3 P6 Reset Value: --00h ...
Page 80
... ST10F269 DP6.y Port Direction Register DP6 Bit y DP6 Port line P6 input (high impedance) DP6 Port line P6 output ODP6 (F1CEH / E7H ODP6.y Port 6 Open Drain Control Register Bit y ODP6 Port line P6.y output driver in push-pull mode ODP6 Port line P6.y output driver in open drain mode 12 ...
Page 81
... CS0 will be in push/pull output driver mode directly after reset. 1 MUX MUX "0" "1" MUX 0 Alternate Function Enable Alternate 1 Data Output MUX 0 1 MUX 0 ST10F269 P6.y Output Buffer Clock Input Latch y = (0... 81/160 ...
Page 82
... ST10F269 Figure 38 : Block Diagram of Pin P6.5 (HOLD) Write ODP6.5 Open Drain Latch Read ODP6.5 Write DP6.5 Direction Latch Read DP6.5 Write P6.5 Port Output Latch Read P6.5 Alternate Data Input 82/160 Clock 1 MUX Input 0 Latch P6.5/HOLD Output Buffer ...
Page 83
... ODP7 Port line P7.y output driver in open drain mode SFR P7.7 P7 SFR DP7.7 DP7.6 DP7.5 DP7.4 DP7.3 DP7.2 DP7.1 DP7 ESFR ODP7.7 ODP7.6 ODP7.5 ODP7.4 ODP7.3 ODP7.2 ODP7.1 ODP7 ST10F269 Reset Value: --00h P7.5 P7.4 P7.3 P7.2 P7 Reset Value: --00h Reset Value: --00h ...
Page 84
... ST10F269 12.10.1 - Alternate Functions of Port 7 The upper 4 lines of Port 7 (P7.7...P7.4) serve as capture inputs or compare (CC31IO...CC28IO) for the CAPCOM2 unit. The usage of the port lines by the CAPCOM unit, its accessibility via software and the precautions are the same as described for the Port 2 lines. ...
Page 85
... Latch Read P7.y EXOR the alternate data output with the port latch output, which allows to use the alternate data directly or inverted at the pin driver. Alternate Data Output =1 Port Data Output EXOR 1 MUX 0 ST10F269 P7.y/POUTy Output Buffer Clock Input y = 0...3 Latch 85/160 ...
Page 86
... ST10F269 Figure 41 : Block Diagram of Port 7 Pins P7.7...P7.4 Write ODP7.y Open Drain Latch Read ODP7.y Write DP7.y Direction Latch Read DP7.y 1 MUX Alternate 0 Data Output Write Port P7.y Compare Trigger Read P7.y 86/160 Output Latch 1 1 MUX 0 Alternate Latch Data Input ...
Page 87
... ODP8. SFR P8.7 P8 SFR DP8.7 DP8.6 DP8.5 DP8.4 DP8.3 DP8.2 DP8.1 DP8 ESFR ODP8.7 ODP8.6 ODP8.5 ODP8.4 ODP8.3 ODP8.2 ODP8.1 ODP8 ST10F269 Reset Value: --00h P8.5 P8.4 P8.3 P8.2 P8 Reset Value: --00h Reset Value: --00h ...
Page 88
... ST10F269 12.11.1 - Alternate Functions of Port 8 The 8 lines of Port 8 serve as capture inputs or as compare outputs (CC23IO...CC16IO) for the CAPCOM2 unit. The usage of the port lines by the CAPCOM unit, its accessibility via software and the precautions are the same as described for the Port 2 lines. ...
Page 89
... P8.7...P8.0 (CC23IO...CC16IO) combine internal bus data and alternate data output before the port latch input the Port 2 pins. Output Latch 1 1 MUX 0 Alternate Latch Data Input Alternate Pin Data Input ST10F269 P8.y CCzIO Output Buffer Clock Input Latch y = (7... (16...23) 89/160 ...
Page 90
... The A/D converter of the ST10F269 supports different conversion modes : – Single channel single conversion : the analog level of the selected channel is sampled once and converted. The result of the conversion is stored in the ADDAT register. – ...
Page 91
... Serial Port Control Shift Clock Receive Shift Register Receive Buffer Transmit Buffer Register S0RBUF Register S0TBUF Internal Bus ) is supported CPU 16 S0PE S0OE Receive Interrupt S0RIR Request Transmit Interrupt S0TIR Request Error Interrupt S0EIR Request Transmit Shift Pin Register TXD0 / P3.10 Output ST10F269 91/160 ...
Page 92
... ST10F269 Asynchronous Mode Baud rates For asynchronous operation, the Baud rate generator provides a clock with 16 times the rate of the established Baud rate. Every received bit is sampled at the 7th, 8th and 9th cycle of this clock. The Baud rate for asynchronous operation of serial channel ASC0 and the required reload ...
Page 93
... ASCO in Synchronous Mode In synchronous mode, data are transmitted or received synchronously to a shift clock which is generated by the ST10F269. Half-duplex communication Baud (at 40MHz of f Figure 45 : Synchronous Mode of Serial Channel ASC0 CPU Clock S0R S0REN S0OEN Output S0LB TDX0/P3.10 Pin Input/Output Receive RXD0/P3.11 ...
Page 94
... ST10F269 Synchronous Mode Baud Rates For synchronous operation, the Baud rate generator provides a clock with 4 times the rate of the established Baud rate. The Baud rate for synchronous operation of serial channel ASC0 can be determined by the following formula: (S0BRL) represents the content of the reload register, taken as unsigned 13-bit integers, (S0BRS) represents the value of bit S0BRS (‘ ...
Page 95
... High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible communication between the ST10F269 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC itself (master ...
Page 96
... ST10F269 Baud Rate Generation The Baud rate generator is clocked by f timer is counting downwards and can be started or stopped through the global enable bit SSCEN in register SSCCON. Register SSCBR is the dual-function Baud Rate register. Reading SSCBR, while the SSC is enabled, returns the content of the timer. Reading SSCBR, while the SSC is disabled, returns the programmed reload value ...
Page 97
... Bytes (1M Byte per CS line). 15.2 - CAN Bus Configurations Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F269 is able to support these 2 cases. Single CAN Bus The single CAN ...
Page 98
... RxD TxD * CAN Transceiver CAN_H CAN_H CAN bus * Open drain output 98/160 Multiple CAN Bus The ST10F269 provides 2 CAN interfaces to support such kind of bus configuration as shown in Figure 49. Figure 49 : Connection to Two Different CAN Buses (e.g. for gateway application) * +5V 2.7k CAN_H CAN_H CAN2 ...
Page 99
... RTCOFF bit of RTCCON register, the user may switch off the clock oscillator when entering the power down mode RTCAI RTCSI RTCCON Basic Clock IT Programmable PRESCALER Register RTCAL RTCPH Reload = RTCDH RTCL ST10F269 CCxIC - - - - - - Clock Oscillator RTCPL RTCDL /64 20 bit DIVIDER 99/160 ...
Page 100
... ST10F269 16.1 - RTC registers 16.1.1 - RTCCON: RTC Control Register The functions of the RTC are controlled by the RTCCON control register. If the RTOFF bit is set, the RTC dividers and counters clock is disabled and registers can be written, when the ST10 chip enters power down mode the clock oscillator will be switch off. The RTC has 2 interrupt sources, one is triggered every basic clock period, the other one is the alarm ...
Page 101
... PRESCALER register, the new value is loaded in the DIVIDER. RTCDL (EC0Ah RTCDH (EC0Ch Note: Those registers are not reset, and are read only. XBUS RTCPL RW XBUS RESERVED RTCPL bit word counter XBUS RTCDL R XBUS RESERVED ST10F269 Reset Value: XXXXh Reset Value: --- RTCPH Reset Value: XXXXh Reset Value: --- RTCDH 101/160 ...
Page 102
... ST10F269 When RTCD increments to reach 00000h, The 20-bit word stored into RTCPH, RTCPL registers is loaded in RTCD. Figure 53 : DIVIDER Counters RTCDH Bit 15 to bit 4 of RTCPH and RTCDH are not used. When reading, the return value of those bit will be zeros. 16.1.4 - RTCH & RTCL: RTC Programmable COUNTER Registers The RTC has 2 x 16-bit programmable counters which count rate is based on the basic time reference (for example 1 second) ...
Page 103
... Alarm interrupt request (RTCAI) is linked with EXI3SS. 3. Timed interrupt request (RTCSI) is linked with EXI2SS. XBUS RTCAL RW XBUS RTCAH RW ESFR EXI4ES EXI3ES ESFR EXI4SS EXI3SS Reset Value: XXXXh Reset Value: XXXXh Reset Value: 0000h EXI2ES EXI1ES RW RW Reset Value: 0000h EXI2SS EXI1SS ST10F269 EXI0ES EXI0SS RW 103/160 ...
Page 104
... ST10F269 Interrupt control registers are common with CAPCOM1 Unit: CC10IC (RTCSI) and CC11IC (RTCAI). CCxIC CC10IC: FF8Ch/C6h CC11IC: FF8Eh/C7h Source of interrupt Request Flag External interrupt 2 CC10IR External interrupt 3 CC11IR 104/160 SFR CCxIR CCxIE RW RW Enable Flag Interrupt Vector CC10IE CC10INT CC11IE ...
Page 105
... Notes: 1. More than one reset indication flag may be set. After EINIT, all flags are cleared. 2. Power-on is detected when a rising edge from V 3. These bits cannot be directly modified by software. SFR PONR LHWR SHWR HR /2. CPU /128. CPU = > 2 recognized on the internal 3.3V supply ST10F269 Reset Value: 00xxh SWR WDTR WDTIN 105/160 0 RW ...
Page 106
... ST10F269 The PONR flag of WDTCON register is set if the output voltage of the internal 3.3V supply falls below the threshold (typically 2V) of the power-on detection circuit. This circuit is efficient to detect major failures of the external 5V supply but if the internal 3.3V supply does not drop under 2 volts, the PONR flag is not set ...
Page 107
... RSTIN pin is low or when RSTIN pin TCL 5 TCL Reset Configuration Latching point of PORT0 for system start-up configuration ST10F269 Conditions Power-on t > 1040 TCL RSTIN 4 TCL < t < 1038 TCL RSTIN WDT overflow SRST execution voltage drops below the RPD 9 1st Instruction External Fetch EXTERNAL FETCH 107/160 ...
Page 108
... ST10F269 Figure 55 : Asynchronous Reset Sequence Internal Fetch CPU Clock Asynchronous Reset Condition RSTIN RPD RSTOUT PORT0 PLL factor latch command Internal reset signal INTERNAL FETCH Flash read signal Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on ...
Page 109
... RSTIN pin level is sampled high while RPD level is high. 1 1024 TCL 2) Internally pulled low If V > 2.5V Asynchronous RPD 3) Reset is not entered. Reset Configuration voltage drops below the threshold voltage (typically 2.5V for 5V operation), the the RPD ST10F269 TCL TCL Latching point of PORT0 ...
Page 110
... ST10F269 The short hardware reset ends and the MCU restarts.To be processed as a short hardware reset, the external RSTIN signal must last a maximum of 1038 TCL (4 TCL + 10 TCL + 1024 TCL). The system configuration is latched from PORT0 after a duration of 8 TCL / 4 CPU clocks (6 TCL / 3 CPU clocks if PLL is bypassed) and in case of external fetch, ALE, RD and R/W pins are driven to their inactive level ...
Page 111
... If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end of the reset sequence. This pull-up charges the capacitor connected to RPD pin. If the bidirectional reset function is not used, the simplest way to reset ST10F269 is to connect external components as shown in Figure 59. It works with reset from application (hardware or manual) and with power-on ...
Page 112
... On power-on totaly discharged, a low level on RPD pin forces an asynchronous hardware reset. C0 capacitor starts to charge throught R0 and at the end of reset sequence ST10F269 restarts. RPD pin threshold is typically 2.5V. Depending on the delay of the next applied reset, the MCU can enter a synchronous reset or an asynchronous reset ...
Page 113
... CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BYTDIS X WRCFG BUS ALE - BTYP 4 4 ACT0 CTL0 1 To Port 6 Logic X External Hardware a) Manual hardware reset1 b) For automatic power-up and interruptible power-down mode V DD External D1 Hardware External Reset Source PORT0 BSL BTYP Internal X ST10F269 - - - - - - ADP EMU Internal Internal 113/160 ...
Page 114
... ST10F269 19 - POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction have been implemented in the ST10F269. In Idle mode only CPU is stopped, while peripheral still operate. In Power Down mode both CPU and peripherals are stopped. Both mode are software activated by a protected instruction and are terminated in different ways as described in the following sections ...
Page 115
... CCxIC register) remains set until it is cleared by software. Note: Reset Value: 0000h EXI2ES EXI1ES RW RW Due to the internal pipeline, instruction that follows the intruction is executed before the CPU performs a call of the interrupt service routine when exiting power-down mode ST10F269 1 0 EXI0ES RW the PWRDN 115/160 ...
Page 116
... ST10F269 Figure 62 : Simplified Powerdown Exit Circuitry enter PowerDown external interrupt reset Figure 63 : Powerdown Exit Sequence When Using an External Interrupt (PLL x 2) XTAL1 CPU clk Internal Powerdown signal External Interrupt RPD ExitPwrd (internal) 116/160 V DD stop pll D Q stop oscillator System clock ...
Page 117
... SPECIAL FUNCTION REGISTER OVERVIEW The following table lists all SFRs which are implemented in the ST10F269 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. ...
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... ST10F269 Table 31 : Special Function Registers Listed by Name (continued) Physical Name address CC9 FE92h CC9IC b FF8Ah CC10 FE94h CC10IC b FF8Ch CC11 FE96h CC11IC b FF8Eh CC12 FE98h CC12IC b FF90h CC13 FE9Ah CC13IC b FF92h CC14 FE9Ch CC14IC b FF94h CC15 FE9Eh CC15IC b FF96h CC16 FE60h ...
Page 119
... MAC Unit Accumulator - Low Word EEh MAC Unit Control Word 87h CPU Multiply Divide Control Register 06h CPU Multiply Divide Register – High Word 07h CPU Multiply Divide Register – Low Word Description ST10F269 Reset value 0000h - - 00h 0000h - - 00h 0000h 0000h 0000h ...
Page 120
... ST10F269 Table 31 : Special Function Registers Listed by Name (continued) Physical Name address MRW b FFDAh MSW b FFDEh ODP2 b F1C2h E ODP3 b F1C6h E ODP4 b F1CAh E ODP6 b F1CEh E ODP7 b F1D2h E ODP8 b F1D6h E ONES b FF1Eh P0L b FF00h P0H b FF02h P1L b FF04h P1H b FF06h P2 b FFC0h P3 b FFC4h ...
Page 121
... SSC Transmit Buffer (write only) B9h SSC Transmit Interrupt Control Register 0Ah CPU Stack Overflow Pointer Register 0Bh CPU Stack Underflow Pointer Register 89h CPU System Configuration Register Description ST10F269 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...
Page 122
... ST10F269 Table 31 : Special Function Registers Listed by Name (continued) Physical Name address T0 FE50h T01CON b FF50h T0IC b FF9Ch T0REL FE54h T1 FE52h T1IC b FF9Eh T1REL FE56h T2 FE40h T2CON b FF40h T2IC b FF60h T3 FE42h T3CON b FF42h T3IC b FF62h T4 FE44h T4CON b FF44h T4IC b FF64h T5 FE46h T5CON b FF46h ...
Page 123
... Device Identifier - 10Dh: ST10F269 identifier. 1 IDMEM (F07Ah / 3Dh MEMTYP R Internal Memory Size is calculated using the following formula: MEMSIZE Size = 4 x [MEMSIZE] (in K Byte) - 040h for ST10F269 (256K Byte) Internal Memory Type - 3h for ST10F269 (Flash memory). MEMTYP 1 IDPROG (F078h / 3Ch PROGVPP R PROGVDD ...
Page 124
... ST10F269 20.2 - System Configuration Registers The ST10F269 has registers used for different configuration of the overall system. These registers are described below. SYSCON (FF12h / 89h STKSZ ROMS1 SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG Notes: 1. These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence. ...
Page 125
... BUS ACT0 ALE CTL0 - SFR BUSACT1 ALECTL1 SFR BUSACT2 ALECTL2 SFR BUSACT3 ALECTL3 Reset Value: 0xx0h BTYP MTTC0 RWDC0 Reset Value: 0000h BTYP MTTC1 RWDC1 Reset Value: 0000h BTYP MTTC2 RWDC2 Reset Value: 0000h BTYP MTTC3 RWDC3 ST10F269 MCTC MCTC MCTC MCTC RW 125/160 ...
Page 126
... ST10F269 BUSCON4 (FF1Ah / 8Dh CSWEN4 CSREN4 RDYPOL4 RDYEN4 Notes: 1. BTYP (bit 6 and 7) are set according to the configuration of the bit l6 and l7 of PORT0 latched at the end of the reset sequence. 2. BUSCON0 is initialized with 0000h pin is high during reset pin is low during reset, bit BUSACT0 and ALECTRL0 are set (’ ...
Page 127
... RP0H default value is "FFh". 2. These bits are set according to Port 0 configuration during any reset sequence. 3. RP0H is a read only register. ESFR CLKSEL OSC = 0 OSC = 1 OSC = f OSC = OSC = OSC = OSC = OSC Reset Value: --XXH SALSEL CSSEL ST10F269 1 0 WRC 2 R 127/160 ...
Page 128
... ST10F269 EXICON (F1C0h / E0h EXI7ES EXI6ES EXI5ES RW RW EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7... Fast external interrupts disabled: standard mode EXxIN pin not taken in account for entering/exiting Power Down mode Interrupt on positive edge (rising) Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level) ...
Page 129
... CAN1EN and CAN2EN are ’0’ also ’1’: The on-chip Real Time Clock is enabled and can be accessed. SFR Area xxIR - - - xxIE RW RW Function ESFR RTCEN RW ST10F269 Reset Value: --00h ILVL RW Reset Value: --05h XRAM2EN XRAM1EN CAN2EN GLVL RW 0 CAN1EN RW 129/160 ...
Page 130
... ST10F269 When both CAN are disabled via XPERCON setting, then any access in the address range 00’EE00h - 00’EFFFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. P4.4 and P4.7 can be used as General Purpose I/O when CAN2 is not enabled, and P4.5 and P4 ...
Page 131
... Absolute Maximum Ratings. 21.2 - Parameter Interpretation The parameters listed in the following tables represent the characteristics of the ST10F269 and its demands on the system. Where the ST10F269 logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics, is included in the “Symbol” column. ...
Page 132
... Notes: 1. ST10F269 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output current is reduced ...
Page 133
... Partially tested, guaranted by design characterization using 22pF loading capacitors on crystal pins. Figure 64 : Supply / Idle Current as a Function of Operating Frequency I [mA] 100 < -0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The =25°C. and =125° CCmax 120mA I CCtyp 60mA I IDmax [MHz] CPU ST10F269 IDtyp 133/160 ...
Page 134
... ST10F269 21.3.1 - A/D Converter Characteristics , ± 10 -40 to +125°C, 4. Table 32 : A/D Converter Characteristics Symbol V SR Analog Reference voltage AREF V SR Analog input voltage AIN I CC Reference supply current AREF running mode power-down mode C CC ADC input capacitance AIN Not sampling Sampling ...
Page 135
... A complete conversion will take 14 t time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. clock. This allows adjusting the A/D converter of the ST10F269 to the properties of the system: started, first the Fast programming the respective times to their absolute possible minimum ...
Page 136
... For timing purposes a port pin is no longer floating when V It begins to float when a 100mV change from the loaded V 21.4.2 - Definition of Internal Timing The internal operation of the ST10F269 is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations ...
Page 137
... XTAL 8MHz XTAL 1 to 40MHz XTAL f x 1.5 6.66 to 26.66MHz XTAL 2 to 80MHz f x 0.5 XTAL 16MHz XTAL and V IL ST10F269 TCL TCL TCL TCL TCL TCL 1 Notes Default configuration 2 Direct drive CPU clock via prescaler . IH2. 3 137/160 ...
Page 138
... Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. 138/160 21.4.6 - Oscillator Watchdog (OWD) An on-chip watchdog oscillator is implemented in the ST10F269. This feature is used for safety operation with external crystal oscillator (using direct drive mode with or without prescaler). This (i.e. the CPU ...
Page 139
... So for a period of 3 TCL periods = 4 - 3/15 = 3.8% = 3TCL 3.8/100) NOM = 3TCL x 0.962 NOM = 36.075ns (at f CPU 40 and 10MHz f 40MHz. CPU CPU XTAL = XTAL F = 1.5/2,/2.5/3/4/5 max min max – 100 – 2 – – 2 – – – ST10F269 = 40MHz) Unit 139/160 ...
Page 140
... ST10F269 Figure 69 : External Clock Drive XTAL1 21.4.9 - Memory Cycle Variables The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. ...
Page 141
... TCL - 8 TCL - 8 -8 – – TCL + 6 2 TCL -9 TCL -9 – 2 TCL - – 3 TCL - – 3 TCL - – 4 TCL - – 2 TCL - 8 TCL - TCL - 8 TCL - TCL - – 3 TCL - TCL - 10 ST10F269 – ns – ns – ns – ns – – ns – – – ns – ns – ns – – ns 141/160 ...
Page 142
... ST10F269 Table 35 : Multiplexed Bus Characteristics Symbol Parameter t CC ALE fall. edge to RdCS, WrCS 42 (with RW delay ALE fall. edge to RdCS, WrCS 43 (no RW delay Address float after RdCS, 44 WrCS (with RW delay Address float after RdCS, 45 WrCS (no RW delay RdCS to Valid Data In 46 (with RW delay) ...
Page 143
... Figure 70 : External Memory Cycle : Multiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT t ALE t 6 CSx A23-A16 (A15-A8) BHE Read Cycle Address/Data Bus (P0) RD Write Cycle Address/Data Bus (P0) WR WRL WRH Address Address Address Data In Address Data Out ST10F269 143/160 ...
Page 144
... ST10F269 Figure 71 : External Memory Cycle: Multiplexed Mus, With / Without Read / Write Delay, Extended ALE CLKOUT t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 Address/Data Bus (P0) RD Write Cycle Address/Data Bus (P0) WR WRL WRH 144/160 Address t 7 Address Address ...
Page 145
... Figure 72 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT t ALE t A23-A16 (A15-A8) BHE t Read Cycle Address/Data Bus (P0) RdCSx Write Cycle Address/Data Bus (P0) WrCSx Address Address Address Address Data Data Out ST10F269 145/160 ...
Page 146
... ST10F269 Figure 73 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t 5 ALE t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 Address/Data Bus (P0) RdCSx Write Cycle Address/Data Bus (P0) WrCSx 146/160 Address t 7 Address Address ...
Page 147
... TCL = 1 to 40MHz Minimum Maximum TCL - 8 – A TCL - 10 – TCL - 8 – A TCL - 8 – TCL - 9 – TCL - 9 – C – 2 TCL - – 3 TCL - – 3 TCL - – 4 TCL - – – 2 TCL - 8 – TCL - 8 TCL - – C TCL - 8 – – ( – > – – 3 TCL - ST10F269 147/160 ...
Page 148
... ST10F269 Table 36 : Demultiplexed Bus Characteristics Symbol Parameter t CC Latched CS hold after RD Address setup to RdCS, WrCS 82 (with RW-delay Address setup to RdCS, WrCS 83 (no RW-delay RdCS to Valid Data In 46 (with RW-delay RdCS to Valid Data In 47 (no RW-delay RdCS, WrCS Low Time 48 (with RW-delay RdCS, WrCS Low Time ...
Page 149
... Figure 74 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT t ALE CSx A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RD Write Cycle Data Bus (P0) (D15-D8) D7-D0 WR WRL WRH Note: 1. Un-latched CSx = TCL =10 41u Address Data Out 41u 28h t 18 Data ST10F269 149/160 ...
Page 150
... ST10F269 Figure 75 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Extended ALE CLKOUT t ALE t CSx A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RD Write Cycle Data Bus (P0) (D15-D8) D7-D0 WR WRL WRH 150/160 Address Data Data Out ...
Page 151
... Figure 76 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT t ALE A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RdCSx Write Cycle Data Bus (P0) (D15-D8) D7-D0 WrCSx Address Data Data Out ST10F269 151/160 ...
Page 152
... ST10F269 Figure 77 : External Memory Cycle: Demultiplexed Bus, no Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t ALE A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RdCSx Write Cycle Data Bus (P0) (D15-D8) D7-D0 WrCSx 152/160 Address Data Data Out ...
Page 153
... refers to the current bus cycle. F Variable CPU Clock 1/2TCL = MHz Minimum Maximum 2TCL 2TCL TCL – 8.5 – TCL – 9.5 – – 4 – 12.5 – 2 – 2TCL + 10 – 12.5 – 2 – 0 TCL - 12 ST10F269 153/160 ...
Page 154
... ST10F269 Figure 78 : CLKOUT and READY t 32 CLKOUT ALE RD, WR Synchronous READY t 58 Asynchronous READY 3) Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle ...
Page 155
... HOLD HLDA BREQ CSx (P6.x) Others Notes: 1. The ST10F269 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after = -40 to +125° 50pF L Maximum CPU Clock ...
Page 156
... Notes: 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be disactivated without the ST10F269 requesting the bus. 2. The next ST10F269 driven bus cycle may start here. ...
Page 157
... Unit Minimum Maximum 100 8 TCL 262144 TCL – 300 – 300 10 – 10 – 15 – – -2 – 2TCL+12.5 – 4TCL – 2TCL – 305 Last Out Bit t t 307 308 Last.In Bit ST10F269 ns – ns – – ns – ns – ns – ns – ns 157/160 ...
Page 158
... ST10F269 21.4.14.2 Slave mode ±10 0V, CPU clock = 40MHz Symbol Parameter t SR SSC clock cycle time 310 t SR SSC clock high time 311 t SR SSC clock low time 312 SR SSC clock rise time t 313 t SR SSC clock fall time 314 t CC Write data valid after shift edge ...
Page 159
... Temperature range -40°C to +125°C ST10F269 0,10 mm .004 inch Inches (approx) Minimum Typical Maximum 0.010 0.125 0.133 0.009 0.005 1.219 1.228 1.098 1 ...
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