MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 258

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale’s Scalable Controller Area Network (S12MSCANV3)
1. The MSCAN must be in normal mode for this bit to become set.
2. See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states.
3. In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the
4. The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see
5. The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).
6. The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).
7. In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the
8. Not including WUPE, INITRQ, and SLPRQ.
9. TSTAT1 and TSTAT0 are not affected by initialization mode.
10. RSTAT1 and RSTAT0 are not affected by initialization mode.
258
INITRQ
SLPRQ
CPU enters wait (CSWAI = 1) or stop mode (see
Stop
“MSCAN Receiver Interrupt Enable Register
initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode
(SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.
WUPE
Field
2
1
0
Mode”)
(6),(7)
(4)
(5)
.
Wake-Up Enable — This configuration bit allows the MSCAN to restart from sleep mode or from power down
mode (entered from sleep) when traffic on CAN is detected (see
bit must be configured before sleep mode entry for the selected function to take effect.
0 Wake-up disabled — The MSCAN ignores traffic on CAN
1 Wake-up enabled — The MSCAN is able to restart
Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving
mode (see
idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry
to sleep mode by setting SLPAK = 1 (see
cannot be set while the WUPIF flag is set (see
Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN
detects activity on the CAN bus and clears SLPRQ itself.
0 Running — The MSCAN functions normally
1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle
Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see
Section 8.4.4.5, “MSCAN Initialization
synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1
(Section 8.3.2.2, “MSCAN Control Register 1
The following registers enter their hard reset state and restore their default values: CANCTL0
CANRIER
The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be
written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the
error counters are not affected by initialization mode.
When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the
MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN
is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.
Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after
initialization mode is exited, which is INITRQ = 0 and INITAK = 0.
0 Normal operation
1 MSCAN in initialization mode
(10)
Section 8.4.5.5, “MSCAN Sleep
Table 8-3. CANCTL0 Register Field Descriptions (continued)
, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.
S12P-Family Reference Manual, Rev. 1.13
(CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.
Section 8.4.5.2, “Operation in Wait
Mode”). Any ongoing transmission or reception is aborted and
Section 8.3.2.2, “MSCAN Control Register 1
Mode”). The sleep mode request is serviced when the CAN bus is
(CANCTL1)”).
Section 8.3.2.5, “MSCAN Receiver Flag Register
Description
Section 8.4.5.5, “MSCAN Sleep
Mode” and
Section 8.4.5.3, “Operation in
Freescale Semiconductor
(CANCTL1)”). SLPRQ
(8)
Section 8.3.2.6,
, CANRFLG
(CANRFLG)”).
Mode”). This
(9)
,