MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 276

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Figure 8-24
identifiers. The mapping of standard identifiers into the IDR registers is shown in
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
1. Exception: The transmit buffer priority registers are 0 out of reset.
276
Register
0x00X0
0x00X1
0x00X2
0x00X3
Name
IDR0
IDR1
IDR2
IDR3
1. Not applicable for receive buffers
Address
0x00XC
0x00XD
0x00XA
0x00XB
0x00XE
0x00XF
0x00X0
0x00X1
0x00X2
0x00X3
0x00X4
0x00X5
0x00X6
0x00X7
0x00X8
0x00X9
Offset
shows the common 13-byte data structure of receive and transmit buffers for extended
Figure 8-24. Receive/Transmit Message Buffer — Extended Identifier Mapping
W
W
W
W
R
R
R
R
Bit 7
ID28
ID20
ID14
Identifier Register 0
Identifier Register 1
Identifier Register 2
Identifier Register 3
Data Segment Register 0
Data Segment Register 1
Data Segment Register 2
Data Segment Register 3
Data Segment Register 4
Data Segment Register 5
Data Segment Register 6
Data Segment Register 7
Data Length Register
Transmit Buffer Priority Register
Time Stamp Register (High Byte)
Time Stamp Register (Low Byte)
ID6
ID27
ID19
ID13
ID5
Table 8-26. Message Buffer Organization
6
S12P-Family Reference Manual, Rev. 1.13
ID26
ID18
ID12
ID4
5
(1)
Register
SRR (=1)
ID25
ID11
ID3
4
IDE (=1)
ID24
ID10
ID2
3
ID23
ID17
ID9
ID1
2
Figure
Freescale Semiconductor
ID22
ID16
ID8
ID0
1
Access
8-25.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
ID21
ID15
RTR
Bit0
ID7
1
.