MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 282

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MC9S12P32CFT

Manufacturer Part Number
MC9S12P32CFT
Description
MCU 16BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12P32CFT

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Package
48QFN EP
Family Name
HCS12
Maximum Speed
32 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
CAN/SCI/SPI
On-chip Adc
10-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Freescale’s Scalable Controller Area Network (S12MSCANV3)
8.3.3.2
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
The number of bytes to be transmitted or received is determined by the data length code in the
corresponding DLR register.
Module Base + 0x00X4 to Module Base + 0x00XB
282
Module Base + 0x00X2
Module Base + 0x00X3
DB[7:0]
Field
7-0
Reset:
Reset:
Reset:
W
W
R
R
Figure 8-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
W
R
Data bits 7-0
Data Segment Registers (DSR0-7)
x
x
7
7
DB7
x
7
= Unused; always read ‘x’
= Unused; always read ‘x’
Figure 8-32. Identifier Register 2 — Standard Mapping
Figure 8-33. Identifier Register 3 — Standard Mapping
Table 8-33. DSR0–DSR7 Register Field Descriptions
6
x
6
x
DB6
x
6
S12P-Family Reference Manual, Rev. 1.13
5
x
5
x
DB5
x
5
4
x
4
x
DB4
Description
x
4
3
x
3
x
DB3
3
x
DB2
x
x
2
2
2
x
Freescale Semiconductor
DB1
x
x
1
1
1
x
DB0
x
x
0
0
0
x

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