MC9S08GT16ACFBE Freescale Semiconductor, MC9S08GT16ACFBE Datasheet - Page 53

• Manufacturer Part Number: MC9S08GT16ACFBE
• Description: IC MCU 16K FLASH 2K RAM 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT16ACFBE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 36
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Processor Series: S08GT
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

4.4.5
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
4.4.6
The block protection feature prevents the protected region of FLASH from program or erase changes.
Block protection is controlled through the FLASH Protection Register (FPROT). When enabled, block
protection begins at any 512 byte boundary and continues through 0xFFFF. (see
Protection Register (FPROT and
After exit from reset, FPROT is loaded with the contents of the NVPROT location which is in the
nonvolatile register block of the FLASH memory. FPROT cannot be changed directly from application
software so a runaway program cannot alter the block protection settings. Since NVPROT is within the last
512 bytes of FLASH, if any amount of memory is protected, NVPROT is itself protected and cannot be
altered (intentionally or unintentionally) by the application software. FPROT can be written through
background debug commands which allows a way to erase and reprogram a protected FLASH memory.
The block protection mechanism is illustrated below. The FPS bits are used as the upper bits of the last
address of unprotected memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bits as
shown. For example, in order to protect the last 8192 bytes of memory (addresses 0xE000 through
0xFFFF), the FPS bits must be set to 1101 111 which results in the value 0xDFFF as the last address of
unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of
Freescale Semiconductor
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Writing to a FLASH address before the internal FLASH clock frequency has been set by writing
to the FCDIV register
Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
Writing a second time to a FLASH address before launching the previous command (There is only
one write to FLASH for every command.)
Writing a second time to FCMD before launching the previous command (There is only one write
to FCMD for every command.)
Writing to any FLASH control register other than FCMD after writing to a FLASH address
Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41)
to FCMD
Accessing (read or write) any FLASH control register other than the write to FSTAT (to clear
FCBEF and launch the command) after writing the command to FCMD
The MCU enters stop mode while a program or erase command is in progress (The command is
aborted.)
Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with
a background debug command while the MCU is secured (The background debug controller can
only do blank check and mass erase commands when the MCU is secure.)
Writing 0 to FCBEF to cancel a partial command
Access Errors
FLASH Block Protection
NVPROT)”).
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Section 4.6.4, “FLASH
Memory
53