C8051F367-GM Silicon Laboratories Inc, C8051F367-GM Datasheet - Page 70

• Manufacturer Part Number: C8051F367-GM
• Description: IC 8051 MCU 32K FLASH 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F367-GM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 28QFN EP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1649

C8051F360/1/2/3/4/5/6/7/8/9
8.
C8051F36x devices include two on-chip programmable voltage comparators, Comparator0 and
Comparator1, shown in Figure 8.1 and Figure 8.2 (Note: the port pin Comparator inputs differ between
C8051F36x devices. The first Port I/O pin shown is for C8051F360/3 devices).
The comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 and CP1), or an
asynchronous “raw” output (CP0A and CP1A). The asynchronous CP0A and CP1A signals are available
even when the system clock is not active. This allows the Comparators to operate and generate an output
with the device in STOP mode. When assigned to a Port pin, the Comparator outputs may be configured
as open drain or push-pull (see Section “17.2. Port I/O Initialization” on page 187). Comparator0 may also
be used as a reset source (see Section “12.5. Comparator0 Reset” on page 131).
The Comparator inputs are selected in the CPT0MX and CPT1MX registers (SFR Definition 8.2 and SFR
Definition 8.5). The CMXnP1–CMXnP0 bits select the Comparator positive input; the CMXnN1–CMXnN0
bits select the Comparator negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “17.3. General Purpose Port I/O” on page 190).
70
Comparators
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CMX0P1
CMX0P0
Figure 8.1. Comparator0 Functional Block Diagram
P1.4 / P1.0
P2.3 / P1.4
P3.1 / P2.0
P3.5 / P2.4
P1.5 / P1.1
P2.4 / P1.5
P3.2 / P2.1
P3.6 / P2.5
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0OUT
CP0RIF
CP0EN
CP0FIF
CP0 +
CP0 -
CP0MD1
CP0MD0
CP0RIE
CP0FIE
Rev. 1.0
+
-
VDD
GND
CP0RIF
CP0FIF
Decision
Reset
Tree
(SYNCHRONIZER)
D
SET
CLR
Q
Q
0
1
0
1
D
SET
CLR
Q
Q
CP0EN
Crossbar
0
1
EA
0
1
CP0A
Interrupt
CP0
CP0