R5F21274SNFP#U0 Renesas Electronics America, R5F21274SNFP#U0 Datasheet - Page 367
R5F21274SNFP#U0
Manufacturer Part Number
R5F21274SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21274SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21274SNFP#U0R5F21274SNFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
18.3
Figure 18.8
18.4
Figure 18.9
When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate
per pin increases. The sample and hold function is available in all operating modes. Start A/D conversion after
selecting whether the sample and hold circuit is to be used or not.
Figure 18.8 shows a Timing Diagram of A/D Conversion.
Figure 18.9 shows the A/D Conversion Cycles.
Without Sample & Hold
Without Sample & Hold
Sample and hold
Sample and hold
With Sample & Hold
With Sample & Hold
Sample and Hold
A/D Conversion Cycles
Sep 26, 2008
A/D Conversion Mode
disabled
enabled
Timing Diagram of A/D Conversion
A/D Conversion Cycles
Page 348 of 453
Sampling time
Sampling time
4ø AD cycles
4ø AD cycles
10 bits
10 bits
Conversion time of 1st bit
Conversion time of 1st bit
8 bits
8 bits
Conversion
49φAD
59φAD
28φAD
33φAD
Time
Comparison
Comparison
time
time
Conversion time at the 1st bit
Sampling
4φAD
4φAD
4φAD
4φAD
Time
2.5ø AD cycles
Sampling time
Comparison
2nd bit
time
Comparison
2.0φAD
2.0φAD
2.5φAD
2.5φAD
Time
* Repeat until conversion ends
2nd bit
Comparison
Comparison
time
time
Conversion time at the 2nd
Sampling
0.0φAD
2.5φAD
2.5φAD
0.0φAD
Time
bit and the follows
2.5ø AD cycles
* Repeat until conversion ends
Sampling time
Comparison
time
Comparison
2.5φAD
2.5φAD
2.5φAD
2.5φAD
Time
Comparison
time
18. A/D Converter
End process
End process
8.0φAD
8.0φAD
4.0φAD
4.0φAD
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