R5F21274SDFP#U0 Renesas Electronics America, R5F21274SDFP#U0 Datasheet - Page 335
R5F21274SDFP#U0
Manufacturer Part Number
R5F21274SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21274SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21274SDFP#U0R5F21274SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 16.43
16.3.5
The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 16.43 shows a Block Diagram of Noise Canceller.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal
(or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next
circuit. When they do not match, the former value is retained.
f1 (sampling clock)
Sep 26, 2008
Noise Canceller
SCL or SDA
input signal
Block Diagram of Noise Canceller
Page 316 of 453
f1 (sampling clock)
Period of f1
D
Latch
C
Q
D
Latch
C
Q
16. Clock Synchronous Serial Interface
detection
Match
circuit
Internal SCL
or SDA signal
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