R5F21257SYFP#U0 Renesas Electronics America, R5F21257SYFP#U0 Datasheet - Page 238
![MCU 2KB FLASH 48K 52-LQFP](/photos/28/61/286101/52-lqfp_sml.jpg)
R5F21257SYFP#U0
Manufacturer Part Number
R5F21257SYFP#U0
Description
MCU 2KB FLASH 48K 52-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Specifications of R5F21257SYFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 105°C
Package / Case
52-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 14.67
Timer RD Output Control Register
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4
NOTES:
b7 b6 b5 b4
NOTES:
0 0 1
1.
2. If the pin function is set for w aveform output (refer to Tables 14.13 to 14.15 and Tables 14.17 to 14.19), the initial
1.
2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
stops).
output level is output w hen the TRDOCR register is set.
This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
TRDFCR register is set to 1 (external clock input enabled).
Feb 29, 2008
0
b3 b2
b3 b2
Registers TRDOCR and TRDCR0 to TRDCR1 in PWM Mode
b1 b0
b1 b0
0
Bit Symbol
Bit Symbol
TRDOCR
TRDCR0
TRDCR1
Symbol
Symbol
CKEG0
CKEG1
CCLR0
CCLR1
CCLR2
TOA0
TOB0
TOC0
TOD0
TOA1
TOB1
TOC1
TOD1
TCK0
TCK1
TCK2
Page 219 of 485
TRDIOA0 output level select bit
TRDIOB0 output level select bit
TRDIOC0 initial output level select bit
TRDIOD0 initial output level select bit
TRDIOA1 initial output level select bit
TRDIOB1 initial output level select bit
TRDIOC1 initial output level select bit
TRDIOD1 initial output level select bit
Count source select bits
External clock edge select bits
TRDi counter clear select bits
(1)
Address
Bit Name
0140h
0150h
Address
Bit Name
013Dh
(2)
(2)
b2 b1 b0
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRDCLK input
1 1 0 : fOCO40M
1 1 1 : Do not set.
b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set.
Set to 001b (the TRDi register cleared at
compare match w ith TRDGRAi register) in PWM
mode.
(2)
(2)
(2)
(2)
(2)
Set this bit to 0 (enable output) in
PWM mode.
0 : Initial output is inactive
1 : Initial output is active level
Set this bit to 0 (enable output) in
PWM mode.
0 : Inactive level
1 : Active level
level
After Reset
Function
(1)
00h
00h
After Reset
Function
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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