R5F21257SYFP#U0 Renesas Electronics America, R5F21257SYFP#U0 Datasheet - Page 513
![MCU 2KB FLASH 48K 52-LQFP](/photos/28/61/286101/52-lqfp_sml.jpg)
R5F21257SYFP#U0
Manufacturer Part Number
R5F21257SYFP#U0
Description
MCU 2KB FLASH 48K 52-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Specifications of R5F21257SYFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 105°C
Package / Case
52-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Rev.
1.00
REVISION HISTORY
May 31, 2006
Date
45 to 51
Page
20
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Table 4.6 SFR Information(6);
Figure 5.4 OFS Register NOTE2 revised
5.1.1 When Power Supply is Stable (2) revised
5.1.2 Power On (4) revised
Figure 5.5 Example of Hardware Reset Circuit and Operation and Figure
5.6 Example of Hardware Reset Circuit (Usage Example of External
Supply Voltage Detection Circuit) and Operation revised
Figure 5.7 Example of Power-On Reset Circuit and Operation revised
5.3 Voltage Monitor 0 Reset revised
Figure 6.5 Registers VCA1 and VCA2; VCA2 register NOTE6 revised
Figures 7.1 to .7.7 Configuration of Programmable I/O Ports NOTE1 added
Figure 7.9 PDi (i = 0 to 4 and 6) Registers NOTE3 added
Figure 7.11 Registers PUR0 and PUR1; After Reset revised
Table 7.31 Port P3_4/SDA/SCS revised
Table 10.1 Specifications of Clock Generation Circuit revised
Figure 10.1 Clock Generation Circuit revised
Figure 10.2 CM0 Register; NOTE6 deleted and NOTE9 revised
Figure 10.4 OCD Register revised
Figure 10.5 Registers FRA0 and FRA1; FRA0 register NOTE2 revised
Figure 10.6 Registers FRA2, FRA4, and FRA6;
Figure 10.8 VCA2 Register NOTE6 revised
Figure 10.9 Examples of XIN Clock Connection Circuit NOTE1 revised
10.2.2 High-Speed On-Chip Oscillator Clock revised
10.4.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) revised
10.4.9 fC4 and fC32 added
Table 10.2 Settings and Modes of Clock Associated Bits revised
10.5.1.2 Low-Speed Clock Mode revised
10.5.2.2 Entering Wait Mode and 10.5.2.3 Pin Status in Wait Mode
revised
10.5.2.4 Exiting Wait Mode;
Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions revised
10.5.2.4 Exiting Wait Mode;
Figure 10.11 Time between Wait Mode and Interrupt Routine Execution added
10.5.2.5 Reducing the Internal Power Consumption added
Figure 10.12 Handling Procedure of Internal Power Low Consumption
Enabled by VCA20 bit revised
R8C/24 Group, R8C/25 Group Hardware Manual
0143h: “11000000b” → “11100000b” revised
FRA2 register NOTE2 deleted, registers FRA4 and FRA6 added
“When using a peripheral ...instruction is executed.” page changed
“When exiting by a peripheral ... CPU clock supply is started.” →
“When exiting by a peripheral ... CM07 bit in the CM0 register.” revised
C - 9
Description
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