R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 266
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 229 of 802
17.5.1
Notes:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
2. Set the INT2PL bit in the INTEN register to 0 (one edge).
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0101h
When the POL bit in the INT2IC register is set to 0 (falling edge selected), the event input for the INT2 high-level
period is enabled. When the POL bit is set to 1 (rising edge selected), the event input for the INT2 low-level
period is enabled.
Symbol TIOGT1
TEDGSEL TRAIO polarity switch bit
TIOSEL
TOPCR
TOENA
TIOGT0
TIOGT1
Bit
Symbol
TIPF0
TIPF1
Timer RA I/O Control Register (TRAIOC) in Event Counter Mode
b7
0
TRAIO output control bit
TRAO output enable bit
Hardware LIN function select bit Set to 0.
TRAIO input filter select bit
TRAIO event input control bit
TIOGT0
b6
0
Oct 30, 2009
Bit Name
TIPF1
b5
0
TIPF0
(1)
b4
0
0: Count at the rising edge of TRAIO input and
1: Count at the falling edge of TRAIO input and
Set to 0 in event counter mode.
0: Port P11_05
1: TRAO output
b5 b4
b7 b6
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
0 0: Event input always enabled
0 1: Event input enabled at INT2 level
1 0: Event input enabled for “L” period of TRCIOD
1 1: Do not set.
TIOSEL
TRAO output starts at low
TRAO output starts at high
(timer RC output)
b3
0
TOENA
b2
0
Function
TOPCR TEDGSEL
b1
0
b0
0
(2)
17. Timer RA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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