R5F2L3A7ANFP#U1 Renesas Electronics America, R5F2L3A7ANFP#U1 Datasheet - Page 566
R5F2L3A7ANFP#U1
Manufacturer Part Number
R5F2L3A7ANFP#U1
Description
MCU FLASH 48+4KB 64LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L3A7ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 529 of 802
Table 24.10
Note:
U2TB
U2RB
U2BRG
U2MR
U2C0
U2C1
U2SMR
U2SMR2 IICM2
U2SMR3 b0, b2, b4,
Register
1. Set the bits not listed in this table to 0 when writing to the above registers in I
(1)
(1)
(1)
b0 to b7
b0 to b7
b8
OER
b0 to b7
SMD2 to SMD0 Set to 010b.
CKDIR
IOPOL
CLK0, CLK1
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
IICM
BBS
b3 to b7
CSC
SWC
STAC
SWC2
SDHI
b7
NODC
CKPH
DL0 to DL2
Registers Used and Settings in I
Bit
Set transmit data.
Receive data can be read.
ACK or NACK is set in this bit.
Overrun error flag
Set the transfer rate.
Set to 0.
Set to 0.
Select the count source for the U2BRG
register.
Disabled because CRD = 1.
Transmit register empty flag
Set to 1.
Set to 1.
Set to 0.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Reception complete flag
Disabled
Set to 0.
Set to 1.
Bus busy flag
Set to 0.
Refer to Table 24.12 I
Functions .
Set to 1 to enable clock synchronization.
Set to 1 to fix SCL2 output low at the falling
edge of the 9th bit of clock.
Set to 0.
Set to 1 to forcibly pull SCL2 output low.
Set to 1 to disable SDA2 output.
Set to 0.
Set to 0.
R e f e r t o Ta b l e 2 4 . 1 2 I
Functions .
Set the amount of SDA2 digital delay.
Oct 30, 2009
Master
2
C Mode
2
C Mode (1)
2
C M o d e
Function
Set transmit data.
Receive data can be read.
ACK or NACK is set in this bit.
Overrun error flag
Disabled
Set to 010b.
Set to 1.
Set to 0.
Disabled
Disabled because CRD = 1.
Transmit register empty flag
Set to 1.
Set to 1.
Set to 0.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Reception complete flag
Disabled
Set to 0.
Set to 1.
Bus busy flag
Set to 0.
Refer to Table 24.12 I
Functions .
Set to 0.
Set to 1 to fix SCL2 output low at the falling
edge of the 9th bit of clock.
Set to 1 to initialize UART2 at start
condition detection.
Set to 1 to forcibly pull SCL2 output low.
Set to 1 to disable SDA2 output.
Set to 0.
Set to 0.
Refer to Table 24.12 I
Functions .
Set the amount of SDA2 digital delay.
2
C mode.
24. Serial Interface (UART2)
Slave
2
2
C Mode
C Mode
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