MC68HC908LK24CFU Freescale Semiconductor, MC68HC908LK24CFU Datasheet - Page 325
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MC68HC908LK24CFU
Manufacturer Part Number
MC68HC908LK24CFU
Description
IC MCU 24K FLASH 8MHZ SPI 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908LK24CFUE.pdf
(464 pages)
Specifications of MC68HC908LK24CFU
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908LK24CFU
Manufacturer:
FREESCALE Semiconductor
Quantity:
489
Company:
Part Number:
MC68HC908LK24CFU
Manufacturer:
Freescale Semiconductor
Quantity:
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MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
MMBB — Bus Busy Flag
MMAST — Master Control Bit
MMRW — Master Read/Write
MMBR2–MMBR0 — Baud Rate Select
This flag is set after a start condition is detected (bus busy), and is
cleared when a stop condition (bus idle) is detected.
Reset clears this bit.
This bit is set to initiate a master mode transfer. In master mode, the
module generates a start condition to the SDA and SCL lines,
followed by sending the calling address stored in MMADR.
When the MMAST bit is cleared by MMNAKIF set (no acknowledge)
or by software, the module generates the stop condition to the lines
after the current byte is transmitted.
If an arbitration loss occurs (MMALIF = 1), the module reverts to slave
mode by clearing MMAST, and releasing SDA and SCL lines
immediately.
This bit is cleared by writing "0" to it or by reset.
This bit will be transmitted out as bit 0 of the calling address when the
module sets the MMAST bit to enter master mode. The MMRW bit
determines the transfer direction of the data bytes that follows. When
it is "1", the module is in master receive mode. When it is "0", the
module is in master transmit mode. Reset clears this bit.
These three bits select one of eight clock rates as the master clock
when the module is in master mode.
Since this master clock is derived the CPU bus clock, the user
program should not execute the WAIT instruction when the MMIIC
module in master mode. This will cause the SDA and SCL lines to
hang, as the WAIT instruction places the MCU in wait mode, with CPU
clock is halted. These bits are cleared upon reset.
(See
1 = Start condition detected
0 = Stop condition detected or MMIIC is disabled
1 = Master mode operation
0 = Slave mode operation
1 = Master mode receive
0 = Master mode transmit
Table 15-2 . Baud Rate
Multi-Master IIC Interface (MMIIC)
Select.)
Multi-Master IIC Interface (MMIIC)
Multi-Master IIC Registers
Data Sheet
325
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