MC68HC705C8AFNE Freescale Semiconductor, MC68HC705C8AFNE Datasheet - Page 56
![IC MCU 8BIT 44-PLCC](/photos/39/70/397062/plcc-44_sml.jpg)
MC68HC705C8AFNE
Manufacturer Part Number
MC68HC705C8AFNE
Description
IC MCU 8BIT 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet
1.MC68HC705C8AB.pdf
(222 pages)
Specifications of MC68HC705C8AFNE
Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
304 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Processor Series
HC705C
Core
HC05
Data Bus Width
8 bit
Data Ram Size
304 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
24
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC705C8AFNE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Interrupts
4.3.6 SPI Interrupts
Technical Data
56
The serial peripheral interrupt (SPI) can generate these interrupts:
Setting the I bit in the CCR disables all SPI interrupts.
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Freescale Semiconductor, Inc.
For More Information On This Product,
SCI Receiver Overrun Interrupt — The overrun bit (OR)
indicates that a received byte is lost because software has not
read the previously received byte. OR becomes set when a byte
shifts into the receive shift register before software reads the word
already in the SCI data register. OR generates an interrupt
request if the receive interrupt enable bit (RIE) is set also.
SCI Receiver Input Idle Interrupt — The receiver input idle bit
(IDLE) indicates that the SCI receiver input is not receiving data.
IDLE becomes set when 10 or 11 consecutive logic 1s appear on
the receiver input. IDLE generates an interrupt request if the idle
line interrupt enable bit (ILIE) is set also.
SPI transmission complete interrupt
SPI mode fault interrupt
SPI Transmission Complete Interrupt — The SPI flag bit (SPIF)
in the SPI status register indicates the completion of an SPI
transmission. SPIF becomes set when a byte shifts into or out of
the SPI data register. SPIF generates an interrupt request if the
SPIE bit is set also.
SPI Mode Fault Interrupt — The mode fault bit (MODF) in the SPI
status register indicates an SPI mode error. MODF becomes set
when a logic 0 occurs on the PD5/SS pin while the master bit
(MSTR) in the SPI control register is set. MODF generates an
interrupt request if the SPIE bit is set also.
Go to: www.freescale.com
Interrupts
MC68HC705C8A — Rev. 3
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