MC68HC705C8AFNE Freescale Semiconductor, MC68HC705C8AFNE Datasheet - Page 62

• Manufacturer Part Number: MC68HC705C8AFNE
• Description: IC MCU 8BIT 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8AFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 304 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Resets
5.3.1 Power-On Reset (POR)
5.3.2 External Reset
5.3.3 Programmable and Non-Programmable COP Watchdog Resets
Technical Data
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A positive transition on the V
The POR is strictly for the power-up condition and cannot be used to
detect drops in power supply voltage.
A 4064 t
active allows the clock generator to stabilize. If the RESET pin is at
logic 0 at the end of 4064 t
until the signal on the RESET pin goes to logic 1.
The minimum time required for the MCU to recognize a reset is 1 1/2
t
as an external reset and not as a COP or clock monitor reset, the RESET
pin must be low for eight t
is sampled. If the pin is still low, an external reset has occurred. If the
input is high, then the MCU assumes that the reset was initiated
internally by either the COP watchdog timer or by the clock monitor. This
method of differentiating between external and internal reset conditions
assumes that the RESET pin will rise to a logic 1 less than two t
its release and that an externally generated reset should stay active for
at least eight t
A timeout of a COP watchdog generates a COP reset. A COP watchdog,
once enabled, is part of a software error detection system and must be
cleared periodically to start a new timeout period.
The MC68HC705C8A has two different COP watchdogs for compatibility
with devices such as the MC68HC705C8 and the MC68HC05C4A:
One COP has four programmable timeout periods and the other has a
fixed non-programmable timeout period.
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1. Programmable COP watchdog reset
2. Non-programmable COP watchdog
Freescale Semiconductor, Inc.
. However, to guarantee that the MCU recognizes an external reset
For More Information On This Product,
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Go to: www.freescale.com
(internal clock cycle) delay after the oscillator becomes
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.
Resets
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DD
. After six t
, the MCU remains in the reset condition
pin generates a power-on reset (POR).
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, the input on the RESET pin
MC68HC705C8A — Rev. 3
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after