MCIMX353CJQ5C Freescale Semiconductor, MCIMX353CJQ5C Datasheet - Page 121

• Manufacturer Part Number: MCIMX353CJQ5C
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX353CJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.9.23
This section describes the electrical information of the UART module.
4.9.23.1
The following subsections give the UART transmit and receive timings in RS-232 serial mode.
4.9.23.1.11 UART Transmitter
Figure 97
Table 79
Freescale Semiconductor
SS25
SS26
SS28
SS30
SS32
SS34
SS35
SS36
SS40
SS41
(output)
ID
TXD
lists the UART RS-232 serial mode transmit timing characteristics.
depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format.
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Rx) CK high to FS (bl) high
(Rx) CK high to FS (bl) low
(Rx) CK high to FS (wl) high
(Rx) CK high to FS (wl) low
(Tx/Rx) External FS rise time
(Tx/Rx) External FS fall time
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
UART Electrical
UART RS-232 Serial Mode Timing
Table 78. SSI Receiver with External Clock Timing Parameters (continued)
Start
UA1
Bit
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Figure 97. UART RS-232 Serial Mode Transmit Timing Diagram
Bit 0
Bit 1
Bit 2
Parameter
Bit 3
UA1
Bit 4
Bit 5
Bit 6
Bit 7
Possible
–10.0
–10.0
Min.
36.0
10.0
10.0
10.0
Par Bit
Parity
2.0
UA1
—
—
—
Bit
STOP
UA1
BIT
Max.
15.0
15.0
6.0
6.0
6.0
—
—
—
—
—
Next
Start
Bit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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