MCIMX353CJQ5C Freescale Semiconductor, MCIMX353CJQ5C Datasheet - Page 46

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MCIMX353CJQ5C

Manufacturer Part Number
MCIMX353CJQ5C
Description
MULTIMEDIA PROCESSOR 400-MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Datasheet

Specifications of MCIMX353CJQ5C

Core Processor
ARM11
Core Size
32-Bit
Speed
532MHz
Connectivity
1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
400-MAPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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46
1
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Table 41
SD10
SD7
SD8
SD9
ID
and
Address hold time
SDRAM access time
Data out hold time
Active to read/write command period
Table
SDR SDRAM CLK parameters are measured from the 50% point—that is,
high is defined as 50% of signal value and low is defined as 50% of signal
value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
42.
1
Table 33
Parameter
indicates SDRAM requirements. All output signals
NOTE
Symbol
tOH
tRC
tAH
tAC
Min.
1.8
1.2
10
Freescale Semiconductor
Max.
6.47
clock
Unit
ns
ns
ns

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