M30800SAGP#U5 Renesas Electronics America, M30800SAGP#U5 Datasheet - Page 105

• Manufacturer Part Number: M30800SAGP#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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10.3 Hardware Interrupts
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Special interrupts and peripheral function interrupts are available as hardware interrupts.
10.3.1 Special Interrupts
10.3.2 Peripheral Function Interrupt
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Special interrupts are non-maskable interrupts.
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10.3.1.1 NMI Interrupt
10.3.1.2 Watchdog Timer Interrupt
10.3.1.3 Oscillation Stop Detection Interrupt
10.3.1.4 Single-Step Interrupt
10.3.1.5 Address Match Interrupt
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The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal
to a low-level ("L") signal. Refer to 10.8 NMI Interrupt for details.
The watchdog timer interrupt occurs when a count source of the watchdog timer underflows. Refer to
11. Watchdog Timer for details.
The oscillation stop detection interrupt occurs when the microcomputer detects a main clock oscilla-
tion stop. Refer to 8. Clock Generation Circuit for details.
Do not use the single-step interrupt. For development support tool only.
The address match interrupt occurs immediately before executing an instruction that is stored into an
address indicated by the RMADi register (i=0 to 7) when the AIERi bit in the AIER register is set to "1"
(address match interrupt enabled). Set the starting address of the instruction in the RMADi register.
The address match interrupt does not occur when a table data or addresses of the instruction other
than the starting address, if the instruction has multiple addresses, is set. Refer to 10.10 Address
Match Interrupt for details.
The peripheral function interrupt occurs when a request from the peripheral functions in the microcom-
puter is acknowledged. The peripheral function interrupts and software interrupt numbers 8 to 48 for
the INT instruction use the same interrupt vector table. The peripheral function interrupt is a maskable
interrupt.
See Table 10.2 about how the peripheral function interrupt occurs. Refer to the descriptions of each
function for details.
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10. Interrupts