MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 148

• Manufacturer Part Number: MC908MR32CFUE
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR32CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 6
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pulse-Width Modulator for Motor Control (PWMMC)
12.9.5 PWM Control Register 2
PWM control register 2 (PCTL2) controls the PWM load frequency, the PWM correction method, and the
PWM counter prescaler. For ease of software and to avoid erroneous PWM periods, some of these
register bits are buffered. The PWM generator will not use the prescaler value until the LDOK bit has been
set, and a new PWM cycle is starting. The correction bits are used at the beginning of each PWM cycle
(if the ISENSx bits are configured for software correction). The load frequency bits are not used until the
current load cycle is complete.
See
LDFQ1 and LDFQ0 — PWM Load Frequency Bits
IPOL1 — Top/Bottom Correction Bit for PWM Pair 1 (PWMs 1 and 2)
148
These buffered read/write bits select the PWM CPU load frequency according to
This buffered read/write bit selects which PWM value register is used if top/bottom correction is to be
achieved without current sensing.
Figure
1 = Use PWM value register 2.
0 = Use PWM value register 1.
12-40.
Address:
Reset:
The user should initialize this register before enabling the PWM.
When reading these bits, the value read is the buffer value (not necessarily
the value the PWM generator is currently using).
The LDFQx bits take effect when the current load cycle is complete
regardless of the state of the load okay bit, LDOK.
Reading the LPFQx bit reads the buffered values and not necessarily the
values currently in effect.
Read:
Write:
LDFQ1
$0021
Bit 7
0
Reload Frequency Bits
Figure 12-40. PWM Control Register 2 (PCTL2)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
LDFQ1 and LDFQ0
= Unimplemented
LDFQ0
6
0
Table 12-8. PWM Reload Frequency
00
01
10
11
5
0
0
IPOL1
NOTE
NOTE
NOTE
Bold
4
0
= Buffered
IPOL2
3
0
PWM Reload Frequency
Every 2 PWM cycles
Every 4 PWM cycles
Every 8 PWM cycles
Every PWM cycle
IPOL3
2
0
PRSC1
1
0
Freescale Semiconductor
Table
PRSC0
Bit 0
0
12-8.