MC68HC16Z1CAG25 Freescale Semiconductor, MC68HC16Z1CAG25 Datasheet - Page 217

• Manufacturer Part Number: MC68HC16Z1CAG25
• Description: IC MCU 16BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CAG25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Cpu Family: HC16
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: SCI/SPI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

9.3.1.2 Status Register
9.3.2 QSPI RAM
9.3.2.1 Receive RAM
9.3.2.2 Transmit RAM
M68HC16 Z SERIES
USER’S MANUAL
SPSR contains information concerning the current serial transmission. Only the QSPI
can set the bits in this register. The CPU16 reads SPSR to obtain QSPI status infor-
mation and writes SPSR to clear status flags.
The QSPI contains an 80-byte block of dual-ported static RAM that can be accessed
by both the QSPI and the CPU16. The RAM is divided into three segments: receive
data RAM, transmit data RAM, and command data RAM. Receive data is information
received from a serial device external to the MCU. Transmit data is information stored
for transmission to an external device. Command control data defines transfer param-
eters. Refer to
Data received by the QSPI is stored in this segment to be read by the CPU16. Data
stored in the receive RAM is right-justified. Unused bits in a receive queue entry are
set to zero by the QSPI upon completion of the individual queue entry. The CPU16 can
access the data using byte, word, or long-word transfers.
The CPTQP value in SPSR shows which queue entries have been executed. The
CPU16 can use this information to determine which locations in receive RAM contain
valid data before reading them.
Data that is to be transmitted by the QSPI is stored in this segment and must be written
by the CPU16 in right-justified form. The QSPI cannot modify information in the trans-
mit RAM. The QSPI copies the information to its data serializer for transmission. Infor-
mation remains in the transmit RAM until overwritten.
51E
500
Figure
Freescale Semiconductor, Inc.
RECEIVE
WORD
RAM
RRD
RR0
RR1
RR2
RRE
RRF
For More Information On This Product,
9-3, which shows RAM organization.
QUEUED SERIAL MODULE
Figure 9-3 QSPI RAM
Go to: www.freescale.com
53E
520
TRANSMIT
WORD
RAM
TRD
TR0
TR1
TR2
TRE
TRF
540
54F
COMMAND
BYTE
RAM
CRD
CRE
CRF
CR0
CR1
CR2
QSPI RAM MAP
9-7