MC68HC16Z1CAG25 Freescale Semiconductor, MC68HC16Z1CAG25 Datasheet - Page 280

• Manufacturer Part Number: MC68HC16Z1CAG25
• Description: IC MCU 16BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CAG25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Cpu Family: HC16
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: SCI/SPI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

11.11 Pulse-Width Modulation Unit
11-16
An interrupt request can be made when each of the status flags is set. However, op-
eration of the PAI interrupt depends on operating mode. In event counting mode, an
interrupt is requested when the edge being counted is detected. In gated mode, the
request is made when the PAI input changes from active to inactive state. Interrupt re-
quests are enabled by the PAOVI and PAII bits in the TMSK2 register.
Bits in the pulse accumulator control register (PACTL) control the operation of PACNT.
The PAMOD bit selects event counting or gated operation. In event counting mode,
the PEDGE control bit determines whether a rising or falling edge is detected. In gated
mode, PEDGE specifies the active state of the gate signal. Bits PACLK[1:0] select the
clock source used in gated mode.
PACTL and PACNT are implemented as one 16-bit register, but can be accessed with
byte or word access cycles. Both registers are cleared at reset, but the PAIS and
PCLKS bits show the state of the PAI and PCLK pins.
The PAI pin can also be used for general-purpose input. The logic state of the PAIS
bit in PACTL shows the state of the pin.
The pulse-width modulation (PWM) unit has two output channels, PWMA and PWMB.
A single clock output from the prescaler multiplexer drives a 16-bit counter that is used
to control both channels.
unit.
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 11-6
GENERAL-PURPOSE TIMER
Go to: www.freescale.com
is a block diagram of the pulse-width modulation
M68HC16 Z SERIES
USER’S MANUAL