HD6417020SVX12IV Renesas Electronics America, HD6417020SVX12IV Datasheet - Page 67

MCU 3/5V 0K PB-FREE 100-TQFP

HD6417020SVX12IV

Manufacturer Part Number
HD6417020SVX12IV
Description
MCU 3/5V 0K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6417020SVX12IV

Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417020SVX12IV
Manufacturer:
RENESAS
Quantity:
63
Part Number:
HD6417020SVX12IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Software Standby Mode: To enter the standby mode, set the standby bit SBY (in the standby
control register SBYCR) to 1 and execute a SLEEP instruction. In standby mode, all CPU, on-chip
peripheral module and oscillator functions are halted. CPU internal register contents and on-chip
RAM data are held.
To return from standby mode, use a reset or an external NMI interrupt. For resets, the CPU returns
to ordinary program execution state through the exception processing state when placed in a reset
state during oscillator stabilization time. For NMI interrupts, the CPU returns to ordinary program
execution state through the exception processing state after the oscillator stabilization time has
elapsed. In this mode, power consumption drops markedly, since the oscillator stops.
Table 2.19 Power-Down State
Mode
Sleep
mode
Stand
by
mode
Note: Differs depending on the peripheral module and pin.
44 RENESAS
Conditions
Execute SLEEP
instruction with
SBY bit cleared
to 0 in SBYCR
Execute SLEEP
instruction with
SBY bit set to 1
in SBYCR
Clock CPU
Run
Halt
Halt Run
Halt Halt and
On-chip
Peripheral
Modules
initialize*
State
CPU
Regi-
sters RAM I/O Ports
Held
Held
Held Held
Held Held or
high-Z*
(selectable)
Canceling
1. Interrupt
2. DMA address
3. Power-on
4. Manual reset
1. NMI
2. Power-on
3. Manual reset
error
reset
reset

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