S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 633

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 16-24
identifiers. The mapping of standard identifiers into the IDR registers is shown in
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
1. Exception: The transmit buffer priority registers are 0 out of reset.
Freescale Semiconductor
1. Not applicable for receive buffers
Address
0x00XA
0x00XB
0x00XC
0x00XD
0x00XE
0x00X0
0x00X1
0x00X2
0x00X3
0x00X4
0x00X5
0x00X6
0x00X7
0x00X8
0x00X9
0x00XF
Offset
shows the common 13-byte data structure of receive and transmit buffers for extended
Identifier Register 0
Identifier Register 1
Identifier Register 2
Identifier Register 3
Data Segment Register 0
Data Segment Register 1
Data Segment Register 2
Data Segment Register 3
Data Segment Register 4
Data Segment Register 5
Data Segment Register 6
Data Segment Register 7
Data Length Register
Transmit Buffer Priority Register
Time Stamp Register (High Byte)
Time Stamp Register (Low Byte)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 16-26. Message Buffer Organization
(1)
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Register
Figure
Access
16-25.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
1
633
.