S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 81

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Vector Address
Vector base + $EC
Vector base + $DA
Vector base + $CE
Vector base + $CC
Vector base + $CA
Freescale Semiconductor
Vector base + $E2
Vector base + $D8
Vector base + $D4
Vector base + $D2
Vector base + $D0
Vector base + $C8
Vector base + $C6
Vector base + $C4
Vector base + $C2
Vector base + $C0
Vector base + $F8
Vector base+ $DE
Vector base+ $DC
Vector base+ $EE
Vector base+ $EA
Vector base+ $E8
Vector base+ $E6
Vector base+ $E4
Vector base+ $E0
Vector base+ $D6
Vector base+ $F6
Vector base+ $F4
Vector base+ $F2
Vector base+ $F0
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
(1)
Channel
XGATE
ID
$6D
$6C
$6F
$6E
$6B
$6A
$78
$77
$76
$75
$74
$73
$72
$71
$70
$69
$68
$67
$66
$65
$64
$63
$62
$61
$60
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(2)
Table 1-14. Interrupt Vector Locations (Sheet 1 of 4)
Enhanced capture timer channel 0
Enhanced capture timer channel 1
Enhanced capture timer channel 2
Enhanced capture timer channel 3
Enhanced capture timer channel 4
Enhanced capture timer channel 5
Enhanced capture timer channel 6
Enhanced capture timer channel 7
Enhanced capture timer overflow
Modulus down counter underflow
MC9S12XE-Family Reference Manual Rev. 1.23
Unimplemented instruction trap
Pulse accumulator A overflow
Pulse accumulator input edge
Pulse accumulator B overflow
CRG self-clock mode
Real time interrupt
Interrupt Source
CRG PLL lock
IIC0 bus
Port H
Port J
XIRQ
ATD0
ATD1
SPI0
SCI0
SCI1
SCI6
SWI
IRQ
Mask
None
None
CCR
X Bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
PIEH (PIEH7-PIEH0)
Chapter 1 Device Overview MC9S12XE-Family
ATD0CTL2 (ASCIE)
ATD1CTL2 (ASCIE)
PIEJ (PIEJ7-PIEJ0)
CRGINT(LOCKIE)
CRGINT (SCMIE)
IRQCR (IRQEN)
CRGINT (RTIE)
PACTL (PAOVI)
PBCTL(PBOVI)
MCCTL(MCZI)
(SPIE, SPTIE)
Local Enable
TSRC2 (TOF)
IBCR0 (IBIE)
PACTL (PAI)
SPI0CR1
SCI0CR2
SCI1CR2
SCI6CR2
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
None
None
None
Wake up
STOP
interrupt section
interrupt section
interrupt section
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Refer to CRG
Refer to CRG
Refer to CRG
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Wake up
WAIT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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