S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 763

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 21
Serial Peripheral Interface (S12SPIV5)
21.1
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral
devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.
21.1.1
21.1.2
The SPI includes these distinctive features:
21.1.3
The SPI functions in three modes: run, wait, and stop.
Freescale Semiconductor
Revision
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Number
V05.00
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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Master mode and slave mode
Selectable 8 or 16-bit transfer width
Bidirectional mode
Slave select output
Mode fault error flag with CPU interrupt capability
Double-buffered data register
Serial clock with programmable polarity and phase
Control of SPI operation during wait mode
Introduction
Revision Date
Glossary of Terms
Features
Modes of Operation
24 Mar 2005
MOMI
MOSI
MISO
SISO
SCK
SPI
SS
21.3.2/21-767
Sections
Affected
MC9S12XE-Family Reference Manual , Rev. 1.23
Serial Peripheral Interface
Slave Select
Serial Clock
Master Output, Slave Input
Master Input, Slave Output
Master Output, Master Input
Slave Input, Slave Output
Table 21-1. Revision History
- Added 16-bit transfer width feature.
Description of Changes
763