DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 489

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Function
Peripheral
modules
Notes: “Halted (retained)” means that internal register values are retained. The internal state is
19.3
The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends
according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU
operates on the operating clock ( /2, /4, /8, /16, or /32). On-chip peripheral modules other
than the bus masters always operate on the system clock ( ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
By clearing all of bits SCK2 to SCK0 to 0, a transition is made to high-speed mode at the end of
the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and the LSON
bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by
an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the
SSBY bit set to 1, the LSON bit cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0,
operation shifts to software standby mode. When software standby mode is cleared by an external
interrupt, medium-speed mode is restored.
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, medium-speed mode is cancelled and a transition is made to
hardware standby mode.
“operation suspended.”
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
“Halted (reset)” means that internal register values and internal states are initialized.
PWMX
Keyboard
buffer
controller
RAM
I/O
Medium-Speed Mode
High-
Speed
Function-
ing
Medium-
Speed
Function-
ing
Sleep
Function-
ing
Module
Stop
Function-
ing/Halted
(reset)
Function-
ing
Function-
ing
Watch
Halted
(reset)
Retained
Retained
Rev. 2.00 Mar 21, 2006 page 449 of 518
Sub-
Active
Halted
(reset)
Function-
ing
Function-
ing
Section 19 Power-Down Modes
Sub-
Sleep
Halted
(reset)
Retained
Function-
ing
Software
Standby
Halted
(reset)
Retained
Retained
REJ09B0299-0200
Hardware
Standby
Halted (reset)
Retained
High
impedance