MC9S12XDP512CAG Freescale Semiconductor, MC9S12XDP512CAG Datasheet - Page 622

• Manufacturer Part Number: MC9S12XDP512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDP512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• For Use With: DEMO9S12XDT512E - BOARD DEMO FOR MC9S12XDT512EVB9S12XDP512E - BOARD DEMO FOR MC9S12XDP512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 17 Memory Mapping Control (S12XMMCV2)
17.3.2.4
Read: Anytime
Write: anytime in special modes, one time only in other modes.
This register determines the position of the direct page within the memory map.
Bits [22:16] of the global address will be formed by the GPAGE[6:0] bits in case the CPU executes a global
instruction in direct addressing mode or by the appropriate local address to the global address expansion
(refer to
622
Address: 0x0011
Example 17-2. This example demonstrates usage of the Direct Addressing Mode by a global instruction
DP[15:8]
Reset
Field
7–0
W
R
Expansion of the CPU Local Address
LDAADR
MOVB
MOVB
GLDAA
DP15
Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct
addressing mode. The bits from this register form bits [15:8] of the address (see
Direct Page Register (DIRECT)
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Bit22
EQU $0000
#$80,DIRECT
#$14,GPAGE
<LDAADR
DP14
0
6
Figure 17-9. DIRECT Address Mapping
Table 17-8. DIRECT Field Descriptions
Figure 17-8. Direct Register (DIRECT)
Bit16
MC9S12XDP512 Data Sheet, Rev. 2.21
Global Address [22:0]
DP13
0
5
;Initialize LDADDR with the value of $0000
;Initialize DIRECT register with the value of $80
;Initialize GPAGE register with the value of $14
;Load Accu A from the global address $14_8000
Bit15
CAUTION
Map).
DP12
DP [15:8]
0
4
Description
CPU Address [15:0]
Bit8
DP11
0
3
Bit7
DP10
0
2
Figure
Freescale Semiconductor
Bit0
DP9
1-9).
0
1
DP8
0
0