DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 16
DF2148BTE20
Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20
HD64F2148BTE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev. 3.00 Mar 21, 2006 page xiv of liv
Item
16.4.4 Master
Receive Operation
Figure 16.15 Sample
Flowchart for
Operations in Master
Receive (Receiving a
Single Byte) (WAIT =
1)
Figure 16.16 Example
of Master Receive
Mode Operation
Timing (MLS = ACKB
= 0, WAIT = 1)
16.4.5 Slave Receive
Operation
Figure 16.22 Example
of Slave Receive Mode
Operation Timing (1)
(MLS = ACKB = 0,
HNDS = 0)
Figure 16.23 Example
of Slave Receive Mode
Operation Timing (2)
(MLS = ACKB = 0,
HNDS = 0)
16.6 Usage Notes
Figure 16.35 ICDR
Read and ICCR
Access Riming in
Slave Transmit Mode
Page
453
456
464
464
483
485
487,
488
Revision (See Manual for Details)
Figure 16.15 amended
Figure 16.16 amended
(master output)
(master output)
Figure title amended
Figure title amended
10. Notes on WAIT Function
Description added
Figure 16.35 amended
R/W
14. Notes on Arbitration Lost in Master Mode
Description added
(slave output)
SDA
SCL
SDA
Master tansmit mode
IRIC
No
Read IRIC flag in ICCR
Set ACKB = 1 in ICSR
9
A
Read ICDR
IRIC = 1?
Master receive mode
Yes
Bit 7
1
Bit 6
2
Bit 5
3
Data 1
Bit 4
4
Bit 3
[2] Start receiving. The first read
[3] Wait for a receive wait
[7] Set acknowledge data for
5
Bit 2
is a dummy read.
(Set IRIC at the fall of the 8th clock)
the last reception.
6
Bit 1
7
Bit 0
8
[3]
A
9
[3]
Bit 7
1
Bit 6
2
Data 2
Bit 5
3
Bit 4
4
Bit 3
5
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