DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 648
DF2148BTE20
Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20
HD64F2148BTE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 21 A/D Converter
21.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D
conversion. The ADST bit can be set at the same time as the operating mode or analog input
channel is changed.
21.4.1
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1,
2. When A/D conversion is completed, the result is transferred to the A/D data register
3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to
4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is
21.4.2
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the
first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1).
When two or more channels are selected, after conversion of the first channel ends, conversion of
the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the
selected channels until the ADST bit is cleared to 0. The conversion results are transferred for
storage into the ADDR registers corresponding to the channels.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
below.
Rev. 3.00 Mar 21, 2006 page 592 of 788
REJ09B0300-0300
by software or an external trigger input.
corresponding to the channel.
1 at this time, an ADI interrupt request is generated.
automatically cleared to 0, and the A/D converter enters wait state.
Operation
Single Mode
Scan Mode
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