DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 172
DF2148BTE20
Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20
HD64F2148BTE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 5 Interrupt Controller
5.7.3
If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address
break interrupt can be generated. This address break function generates an interrupt request to the
interrupt controller at prefetch, and determines the priority by the interrupt controller. When an
interrupt is accepted, an interrupt exception handling is activated after the current instruction has
been completed. Note that the interrupt mask control according to the I and UI bits in CCR of the
CPU is invalid to an address break interrupt.
To use the address break function, set each register as follows:
1. Set a break address in the A23 to A1 bits in BAR.
2. Set the BIE bit in ABRKCR to 1 to enable the address break.
When the setting conditions are satisfied, the CMF flag in ABRKCR is set to 1 to request an
interrupt. The interrupt source should be determined by the interrupt handling routine if necessary.
5.7.4
1. In an address break, the break address should be an address where the first byte of the
2. In normal mode, addresses A23 to A16 are not compared.
3. When the branch instructions (Bcc, BSR), jump instructions (JMP, JSR), RST instruction, and
4. An address break interrupt is generated by combining the internal prefetch signal and an
Figure 5.10 shows an example of address timing.
Rev. 3.00 Mar 21, 2006 page 116 of 788
REJ09B0300-0300
When the BIE bit is cleared to 0, an address break is not requested.
instruction exists. Otherwise, a break condition will not be satisfied.
RTE instruction are placed immediately prior to the address specified by BAR, a prefetch
signal to the address may be output to request an address break by executing these instruction.
It is necessary to take countermeasures: do not set a break address to an address immediately
after these instructions, or determine whether interrupt handling is performed by satisfaction of
a normal condition.
address. Therefore, the timing to enter the interrupt exception handling differs according to the
instructions at the specified and at prior addresses and execution cycles.
Operation
Usage Notes
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