DF2148BTE20 Renesas Electronics America, DF2148BTE20 Datasheet - Page 529
DF2148BTE20
Manufacturer Part Number
DF2148BTE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BTE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BTE20
HD64F2148BTE20
HD64F2148BTE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148BTE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 529 of 847
- Download datasheet (5Mb)
16.4.11 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 16.3.7, DDC Switch
Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
The following items are not initialized:
ICDRE and ICDRF internal flags
Transmit/receive sequencer and internal operating clock counter
Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE
and ICDRF flags), DDCSWR)
Internal latches used to retain register read information for setting/clearing flags in ICMR,
ICCR, ICSR, and DDCSWR
The value of the ICMR bit counter (BC2 to BC0)
Generated interrupt sources (interrupt sources transferred to the interrupt controller)
SCL or
SDA input
signal
Sampling
clock
D
Figure 16.29 Block Diagram of Noise Canceler
Sampling clock
System clock
cycle
Latch
C
Q
D
Latch
C
Section 16 I
Q
Rev. 3.00 Mar 21, 2006 page 473 of 788
detector
2
C Bus Interface (IIC) (Optional)
Match
REJ09B0300-0300
Internal
SCL or
SDA
signal
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