HD6473228F10V Renesas Electronics America, HD6473228F10V Datasheet - Page 150

• Manufacturer Part Number: HD6473228F10V
• Description: MCU 5V 32K,PB-FREE 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473228F10V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

7.5 Interrupts
The free-running timer channel can request four types of interrupts: input capture (ICI), output
compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is requested when the
corresponding flag bit is set, provided the corresponding enable bit is also set. Independent signals
are sent to the interrupt controller for each type of interrupt. Table 7-3 lists information about these
interrupts.
Table 7-3. Free-Running Timer Interrupts
Interrupt
ICI
OCIA
OCIB
FOVI
7.6 Noise Canceler
The noise canceler acts as a digital low-pass filter, rejecting high-frequency pulses received at the
input capture (FTI) pin. Figure 7-14 shows a block diagram of the noise canceler.
The noise canceler consists of four latches connected in series, and a circuit that detects when all
four latches contain the same value. The FTI input is sampled on the rising edge of the sampling
clock selected by the NCS1 and NCS0 bits. When all four latches contain the same value, this value
is regarded as valid and output from the noise canceler. If all four latches are not the same, the
noise canceler holds its previous output. Immediately after a reset, the noise canceler output is 0.
To assure capture, the pulse input at the FTI pin must be at least four sampling clock cycles wide.
The noise canceler control register (FNCR) provides a selection of three sampling clock rates and
the option of disabling the noise canceler. Table 7-4 indicates the cycle times of the sampling clock
for various settings.
Description
Requested when ICF and ICIE are set
Requested when OCFA and OCIAE are set
Requested when OCFB and OCIBE are set
Requested when OVF and OVIE are set
142
Priority
High
Low