M30873FHGP#U3 Renesas Electronics America, M30873FHGP#U3 Datasheet - Page 211

• Manufacturer Part Number: M30873FHGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 187 of 587
Figure 15.24
Timer Bi Mode Register (i = 0 to 5)
(Pulse Period Measurement Mode, Pulse Width Measurement Mode)
b7
NOTES:
b6 b5 b4
1. Bits MR1 and MR0 determine the following measurement modes:
2. The MR3 bit is undefined when reset.
3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write to the TBiMR register after the MR3 bit
4. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the
becomes 1 (overflow), while the TBiS bit in TABSR or TBSR register is set to 1 (count starts).
TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Pulse period measurement 1 (bits MR1 and MR0 are set to 00b):
Pulse period measurement 2 (bits MR1 and MR0 bits are set to 01b):
Pulse width measurement (bits MR1 and MR0 bits are set to 10b):
Measures the width between the falling edges of a pulse
Measures the width between the rising edges of a pulse
Measures the width between a falling edge and a rising edge of a pulse, and between a rising edge and a falling edge of a pulse
b3
b2
TB0MR to TB5MR Registers in Pulse Period Measurement Mode, Pulse Width
Measurement Mode
b1
1
b0
0
Bit Symbol
TMOD0
TMOD1
TCK0
TCK1
MR0
MR1
MR2
MR3
Symbol
TB0MR to TB5MR
Operating mode select bits
Measurement mode
select bits
Registers TB0MR and TB3MR:
Registers TB1MR, TB2MR, TB4MR, and TB5MR:
Timer Bi overflow flag
Count source select bits
Set to 0 in pulse period measurement mode, pulse width measurement mode.
Unimplemented.
Write 0. Read as undefined value.
(1)
Bit Name
Address
035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
(2)
b1 b0
1 0: Pulse period measurement mode
b3 b2
0 0: Pulse period measurement 1
0 1: Pulse period measurement 2
1 0: Pulse width measurement
1 1: Do not set to this value
0: No overflow has occurred
1: Overflow has occurred
b7 b6
0 0: f1
0 1: f8
1 0: f2n
1 1: fC32
Pulse width measurement mode
(4)
Function
(3)
After Reset
00XX 0000b
RW
RW
RW
RW
RW
RW
RW
RW
RO
−
15. Timer B