M30873FHGP#U3 Renesas Electronics America, M30873FHGP#U3 Datasheet - Page 378

• Manufacturer Part Number: M30873FHGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 354 of 587
22.3.1
Table 22.7
NOTE:
Waveform generation channel
OUTCi_ j pin
Output waveform
Waveform output start condition
Waveform output stop condition
Interrupt request generation timing An interrupt request is generated at the second clock cycle after the base timer
Selectable function
1. When the INV bit in the GiPOCRj register is set to 1 (output inverted), the “L” width and the “H” width are
The OUTCi_j pin outputs “H” when the base timer value matches the GiPOj register value (i = 1, 2; j = 0 to 7),
and outputs “L” when the base timer is reset.
Table 22.7 lists specifications of single-phase waveform output mode. Figure 22.27 shows an example of
single-phase waveform output mode operation.
inversed.
Single-Phase Waveform Output Mode (Group 1 and Group 2)
Item
Single-Phase Waveform Output Mode Specifications
(1)
Group 1 and 2: channels 0 to 7
Pulse output
• Base timer is not reset:
• Base timer is reset when base timer value matches the GiPO0 register value:
Set both the BTS bit in the GiBCR1 register and the IFEj bit in the GiFE register
to 1
Set either the BTS or IFEj bit to 0
value matches the GiPOj register value.
The POijR bit in the IIOkIR register (k = 0 to 11) becomes 1 (interrupt requested)
when an interrupt request is generated.
• Initial value set function:
• Inverted output function:
Cycle:
“L” width:
“H” width:
Cycle:
“L” width:
“H” width:
(See Figure 11.18 IIO0IR to IIO11IR Registers)
-The INV bit in the GiPOCRj register is set to 0 (output not inverted)
-Bits UD1 and UD0 in G1BCR1 register are set to 00b (counter increment mode)
-The INV bit in the GiPOCRj register is set to 0 (output not inverted)
-Bits UD1 and UD0 in G1BCR1 register are set to 00b (counter increment mode)
Set the initial output level when waveform output is started (determined by the
IVL bit in the GiPOCRj register)
Output the inverted waveform level (determined by the INV bit in the GiPOCRj
register)
m: setting value of the GiPOj register: 0000h to FFFFh
m: setting value of the GiPOj register (0000h to FFFFh)
p: setting value of the GiPO0 register (0001h to FFFDh)
If m ≥ p + 2, the output level is fixed to “L”
65536 - m
p + 2 - m
65536
p + 2
fBTi
fBTi
fBTi
fBTi
fBTi
fBTi
m
m
22. Intelligent I/O (Waveform Generation Function)
Specification