HD6473258P10V Renesas Electronics America, HD6473258P10V Datasheet - Page 133

• Manufacturer Part Number: HD6473258P10V
• Description: MCU 5V 32K PB-FREE 64-DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10V

• Core Size: 8-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• No. Of I/o's: 53
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• Digital Ic Case Style: DIP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/330
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1.3 Input and Output Pins
Table 7-1 lists the input and output pins of the free-running timer module.
Table 7-1. Input and Output Pins of Free-Running Timer Module
Name
Counter clock input
Output compare A
Output compare B
Input capture
7.1.4 Register Configuration
Table 7-2 lists the registers of the free-running timer module.
Table 7-2. Register Configuration
Name
Timer control register
Timer control/status register
Free-running counter (high)
Free-running counter (low)
Output compare register A (high)
Output compare register A (low)
Output compare register B (high)
Output compare register B (low)
Input capture register (high)
Input capture register (low)
FRT noise canceler control register
* Software can write a 0 to clear bits 7 to 4, but cannot write a 1 in these bits.
Abbreviation
FTCI
FTOA
FTOB
FTI
I/O
Input
Output
Output
Input
Abbreviation
TCR
TCSR
FRC (H)
FRC (L)
OCRA (H)
OCRA (L)
OCRB (H)
OCRB (L)
ICR (H)
ICR (L)
FNCR
125
Function
Input of external free-running counter clock
signal
Output controlled by comparator A
Output controlled by comparator B
Input capture trigger
R/W
R/W
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
Initial
value
H’00
H’00
H’00
H’00
H’FF
H’FF
H’FF
H’FF
H’00
H’00
H'FC
Address
H’FF90
H’FF91
H’FF92
H’FF93
H’FF94
H’FF95
H’FF96
H’FF97
H’FF98
H’FF99
H’FFFF