HD6473258P10V Renesas Electronics America, HD6473258P10V Datasheet - Page 65

• Manufacturer Part Number: HD6473258P10V
• Description: MCU 5V 32K PB-FREE 64-DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10V

• Core Size: 8-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• No. Of I/o's: 53
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• Digital Ic Case Style: DIP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/330
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6.3 Power-Down State
The power-down state includes three modes: the sleep mode, the software standby mode, and the
hardware standby mode.
(1) Sleep Mode: The sleep mode is entered when a SLEEP instruction is executed. The CPU
halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to
function.
When an interrupt or reset signal is received, the CPU returns through the exception-handling state
to the program execution state.
(2) Software Standby Mode: The software standby mode is entered if the SLEEP instruction is
executed while the SSBY (Software Standby) bit in the system control register (SYSCR) is set.
The CPU and all on-chip supporting modules halt. The on-chip supporting modules are initialized,
but the contents of the on-chip RAM and CPU registers remain unchanged. I/O port outputs also
remain unchanged.
(3) Hardware Standby Mode: The hardware standby mode is entered when the input at the
STBY pin goes Low. All chip functions halt, including I/O port output. The on-chip supporting
modules are initialized, but on-chip RAM contents are held.
See section 12, “Power-Down State” for further information.
3.7 Access Timing and Bus Cycle
The CPU is driven by the system clock (Ø). The period from one rising edge of the system clock to
the next is referred to as a “state.”
Memory access is performed in a two-or three-state bus cycle as described below. For more
detailed timing diagrams of the bus cycles, see section 15, “Electrical Specifications.”
3.7.1 Access to On-Chip Memory (RAM and ROM)
On-chip ROM and RAM are accessed in a cycle of two states designated T
and T
. Either byte or
1
2
word data can be accessed, via a 16-bit data bus. Figure 3-13 shows the on-chip memory access
cycle. Figure 3-14 shows the associated pin states.
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