DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 12

MCU 5V 128K,PB-FREE 100-TQFP

DF3048X16V

Manufacturer Part Number
DF3048X16V
Description
MCU 5V 128K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3048X16V

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3048X16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev. 7.00 Sep 21, 2005 page x of xxiv
Item
19.5.6 Erasing
Flowchart and
Sample Program
Flowchart for
Erasing Multiple
Blocks
Figure 19.12
Multiple-Block Erase
Flowchart
Page
616
Revision (See Manual for Details)
Figure amended
Erase-verify
next block
Address + 1
address
No
Select erase mode (E bit = 1 in FLMCR)
Clear EBR bit of erase-verified block
Wait initial value setting x = 6.25 ms
No
Dummy write to verify address
(flash memory latches address)
Set top address of block as
Enable watchdog timer
Select erase-verify mode
Disable watchdog timer
(EV bit = 1 in FLMCR)
(EBR1 = EBR2 = 0?)
All blocks erased?
Yes
address in block?
All erased blocks
Yes
Clear
verify address
Wait (t
Wait (t
(read memory)
OK
Clear EV bit
End of erase
Yes
Wait (x) ms
Clear E bit
verified?
Verify
Last
V
VS1
VS2
PP
) s
) s
E
bit
*5
*5
*2
*
3
No good
No
*4
Erasing ends
(clear bits of blocks to be erased to 0)
Double the erase time (x
All erased blocks
Clear erase block registers
verified?
Clear
Yes
Yes
Erase error
5. t
6. The erase time x is successively
n
n
N?
V
z:
t
N:
incremented by the initial set value
value of 10 ms or less should be
set, and the time for one erasure
should be 50 ms or less.
4?
No
VS1
VS2
PP
2n
E
: 4 µs
: 2 s
Erase-verify next block
–1
bit
5 to 10 s
602
(n = 1, 2, 3, 4). An initial
No
2
x)
No
*6
Yes
n + 1
n

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