DF3048X16V Renesas Electronics America, DF3048X16V Datasheet - Page 235

• Manufacturer Part Number: DF3048X16V
• Description: MCU 5V 128K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048X16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.3
In full address mode the A and B channels operate together. Full address mode is selected as
indicated in table 8.4.
8.3.1
A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the
source address register of the transfer, and MARB as the destination address register.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved: they cannot be modified and are always read as 1.
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 8.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
8.3.2
The I/O address registers (IOARs) are not used in full address mode.
Bit
Initial value
Read/Write
Register Descriptions (Full Address Mode)
Memory Address Registers (MAR)
31
I/O Address Registers (IOAR)
—
1
30
—
1
29
—
1
MARR
28
—
1
27
—
1
26
—
1
25
—
1
24
—
1
R/W
23
R/W
22
R/W
21
R/W
MARE
20
Source or destination address
R/W
19
R/W
18
R/W
17
R/W
16
R/W
15
R/W
14
Rev. 7.00 Sep 21, 2005 page 209 of 878
R/W
13
Undetermined
R/W
MARH
12
R/W
11
R/W
10
R/W
9
Section 8 DMA Controller
R/W
8
R/W
7
R/W
6
REJ09B0259-0700
R/W
5
R/W
MARL
4
R/W
3
R/W
2
R/W
1
R/W
0