M30620FCAFP#U5 Renesas Electronics America, M30620FCAFP#U5 Datasheet - Page 381

• Manufacturer Part Number: M30620FCAFP#U5
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30620FCAFP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: M16C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: SIM/UART
• On-chip Adc: 10-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Clock-Synchronous Serial I/O
2-62
Figure 2.4.8. Set-up procedure of transmission in clock-synchronous serial I/O mode (1)
b7
Setting UARTi transmit/receive mode register (i=0 to 2)
0
b7
Setting UARTi transmit/receive control register 0 (i=0 to 2)
0 0
b7
Setting UART transmit/receive control register 2 and UART2 transmit/receive control register 1
Note: Set the corresponding port direction register to “0” .
0
0
0
0
0
0
0 1
0
b0
b0
b0
0
Must be fixed to “001”
Internal/external clock select bit
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Sleep select bit
BRG count source select bit
CLK polarity select bit
Transfer format select bit
CTS/RTS function select bit
(Valid when bit 4 = “0”)
Transmit register empty flag
CTS/RTS disable bit
Data output select bit
0 : Internal clock
Must always be “0” in clock synchronous I/O mode
b1 b0
UART0 transmit interrupt cause select bit
UART1 transmit interrupt cause select bit
Valid when bit 5 = “1”
CLK/CLKS select bit 1
Reserved bit
UART0 transmit/receive mode register
U0MR
UART1 transmit/receive mode register
U1MR
0 0 : f
0 1 : f
1 0 : f
1 1 : Must not be set
0 : CTS function is selected (Note)
0 : Transmission data is output at falling edge
0 : LSB first
UART0 transmit/receive control register 0
U0C0 [Address 03A4
UART1 transmit/receive control register 0
U1C0 [Address 03AC
0 : Data present in transmit register
1 : No data present in transmit register
0 : CTS/RTS function enabled
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
0 : Transmit buffer empty (Tl = 1)
0 : Transmit buffer empty (Tl = 1)
0 : Normal mode (CLK output is CLK1 only)
Must always be set to “0”
UART transmit/receive control register 2
UCON [Address 03B0
(during transmission)
(transmission completed)
of transfer clock and reception data is input
at rising edge
1
8
32
[Address
[Address
is selected
is selected
is selected
03A0
03A8
16
16
16
16
]
]
]
]
16
]
Continued to the next page
b7
b7
0
0
b7
0 0
0
0
0
0
0
0 1
b0
b0
b0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Internal/external clock select bit
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Transmit register empty flag
CTS/RTS disable bit
Must be fixed to “001”
T
BRG count source select bit
CTS/RTS function select bit
(Valid when bit 4 = “0”)
CLK polarity select bit
Transfer format select bit
b1 b0
UART2 transmit/receive mode register
U2MR
0 : Internal clock
UART2 transmit interrupt cause select bit
Data logic select bit
Error signal output enable bit
X
Usually set to “0”
0 0 : f
0 1 : f
1 0 : f
1 1 : Must not be set
0 : CTS function is selected (Note)
0 : Data present in transmit register
1 : No data present in transmit register
0 : CTS/RTS function enabled
0 : Transmission data is output at falling edge
0 : LSB first
UART2 transmit/receive control register 0
U2C0 [Address
0 : Transmit buffer empty (Tl = 1)
0 : No reverse
Must always be “0” in clock synchronous I/O mode
D, R
UART2 transmit/receive control register 1
U2C1 [Address 037D
(during transmission)
(transmission completed)
of transfer clock and reception data is input
at rising edge
X
1
8
32
[Address
D I/O polarity reverse bit
is selected
is selected
is selected
0378
037C
16
16
]
]
16
]
M16C / 62A Group
Mitsubishi microcomputers