HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 452

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
14.2.5
The DMA channel request assign register (CHRAR) is a 16-bit read/write registers that assign
requests from USBF or SIOF to each DMA channel, to each expanded DMA. It is initialized to 0
at power-on reset, or in hardware standby mode or software standby mode. These register values
are initialized to 0s after a power-on reset. The previous value is held in standby mode.
Bits 15 to 12 —DMA Channel 3 Request Assign 3 to 0 (CH3RID3 to CH3RID0): These bits
select DMA requests from DMA channel 3.
Bits 15 to 12:
CH3RID3 to CH3RID0
0000
0001
0010
1001
1010
Rev.6.00 Mar. 27, 2009 Page 394 of 1036
REJ09B0254-0600
Initial value:
Initial value:
DMA Channel Request Assign Register (CHRAR)
R/W:
R/W:
Bit:
Bit:
Description
Unused
USBF (USB function) reception requests to the DMA are selected from
channel 3
USBF (USB function) transmission requests to the DMA are selected
from channel 3
SIOF reception requests to the DMA are selected from channel 3
SIOF transmission requests to the DMA are selected from channel 3
CH3RID3 to CH0RID0
CH1RID3 to CH1RID0
15,14,13,12
7,6,5,4
R/W
R/W
0
0
CH2RID3 to CH2RID0
CH0RID3 to CH0RID0
11,10,9,8
3,2,1,0
R/W
R/W
0
0
(Initial value)