HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 759

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 3—EP3 Stall (EP3 STL): When this bit is set to 1, endpoint 3 is placed in the stall state.
Bit 2—EP2 Stall (EP2 STL): When this bit is set to 1, endpoint 2 is placed in the stall state.
Bit 1—EP1 Stall (EP1 STL): When this bit is set to 1, endpoint 1 is placed in the stall state.
Bit 0—EP0 Stall (EP0 STL): When this bit is set to 1, endpoint 0 is placed in the stall state.
23.5.14 USB Interrupt Enable Register 0 (USBIER0)
USBIER0 enables the interrupt requests indicated in USB interrupt flag register 0 (USBIFR0).
When an interrupt flag is set while the corresponding bit in USBIER0 is set to 1, an interrupt
request is sent to the CPU. The contents of the interrupt event register (INTEVT2) are determined
by the contents of USB interrupt select register 0 (USBISR0).
23.5.15 USB Interrupt Enable Register 1 (USBIER1)
USBIER1 enables the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1).
When an interrupt flag is set while the corresponding bit in USBIER1 is set to 1, an interrupt
request is sent to the CPU. The contents of the interrupt event register (INTEVT2) are determined
by the contents of USB interrupt select register 1 (USBISR1).
23.5.16 USBEP1 Receive Data Size Register (USBEPSZ1)
USBEPSZ1 is the endpoint 1 receive data size register, indicating the amount of data received
from the host. The endpoint 1 FIFO buffer has a dual-FIFO configuration; the receive data size
indicated by this register refers to the currently selected FIFO.
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
BRST
R/W
—
R
7
0
7
0
FULL
EP1
R/W
—
R
6
0
6
0
EP2
R/W
TR
—
R
5
0
5
0
EMPTY
R/W
EP2
—
R
4
0
4
0
Rev.6.00 Mar. 27, 2009 Page 701 of 1036
SETUP
R/W
TS
—
R
3
0
3
0
Section 23 USB Function Controller
EP0o
R/W
EP3
R/W
TS
TR
2
0
2
0
REJ09B0254-0600
EP0i
R/W
EP3
R/W
TR
TS
1
0
1
0
VBUSF
EP0i
R/W
R/W
TS
0
0
0
0