DF2166VT33 Renesas Electronics America, DF2166VT33 Datasheet - Page 153

• Manufacturer Part Number: DF2166VT33
• Description: MCU FLASH 3V 512K 33MHZ 144TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

• When ADMXE = 0
Bit
2
1
0
• When ADMXE = 1
Bit
2
1
0
Bit Name
WC22
WC21
WC20
Bit Name
WC22
WC21
WC20
Initial
Value
1
1
1
Initial
Value
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
CP Extended Area Wait Count 2 to 0
Select the number of program wait states to be inserted for
access to the CP extended area when the CPCSE and
ASTCP bits in BCR2 are set to 1.
If the CP extended area is selected, the WC22 bit must be
cleared to 0.
000: Program wait state is not inserted
001: 1 program wait state is inserted
010: 2 program wait states are inserted
011: 3 program wait states are inserted
100: (Setting prohibited)
101: (Setting prohibited)
110: (Setting prohibited)
111: (Setting prohibited)
Description
Address-Data Multiplex Extended Area Address Cycle Wait
Count 2
Selects the number of program wait states to be inserted
into the address cycle for access to the address-data
multiplex extended area.
0: Program wait state is not inserted
1: 1 program wait state is inserted in the address cycle
CP Extended Area Data Cycle Wait Count 1 and 0
Selects the number of program wait states to be inserted in
the data cycle for access to the CP extended area when the
CPCSE and ASTCP bits in BCR2 are set to 1.
00: Program wait state is not inserted in the data cycle
01: 1 program wait state is inserted in the data cycle
10: 2 program wait states are inserted in the data cycle
11: 3 program wait states are inserted in the data cycle
Rev. 3.00, 03/04, page 111 of 830