R8A77850AADBGV Renesas Electronics America, R8A77850AADBGV Datasheet - Page 1494
R8A77850AADBGV
Manufacturer Part Number
R8A77850AADBGV
Description
IC SUPERH MCU 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850AADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850AADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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29. User Break Controller (UBC)
Notes: 1. If the data value is included in the match conditions, be sure to specify the operand
Rev.1.00 Jan. 10, 2008 Page 1462 of 1658
REJ09B0261-0100
Bit
7, 6
5, 4
3
2, 1
0
2. If the quadword access is specified and the data value is included in the match
3. The OCBI instruction is handled as longword write access without the data value, and
Bit Name
CD
ID
—
RW
CE
size.
conditions, the upper and lower 32 bits of 64-bit data are each compared with the
contents of both the match data setting register and the match data mask setting
register.
the PREF, OCBP, and OCBWB instructions are handled as longword read access
without the data value. Therefore, do not include the data value in the match conditions
for these instructions.
Initial
Value
All 0
All 0
0
All 0
0
R/W
R/W
R/W
R
R/W
R/W
Channel Enable
Description
Bus Select
Specifies the bus to be included in the match
conditions. This bit is valid only when the operand
access cycle is specified as a match condition.
00: Operand bus for operand access
Others: Reserved (setting prohibited)
Instruction Fetch/Operand Access Select
Specifies the instruction fetch cycle or operand access
cycle as the match condition.
00: Instruction fetch cycle or operand access cycle
01: Instruction fetch cycle
10: Operand access cycle
11: Instruction fetch cycle or operand access cycle
Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
Bus Command Select
Specifies the read/write cycle as the match condition.
This bit is valid only when the operand access cycle is
specified as a match condition.
00: Read cycle or write cycle
01: Read cycle
10: Write cycle
11: Read cycle or write cycle
Validates/invalidates the channel. If this bit is 0, all the
other bits in this register are invalid.
0: Invalidates the channel.
1: Validates the channel.
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