R8A77850AADBGV Renesas Electronics America, R8A77850AADBGV Datasheet - Page 842
R8A77850AADBGV
Manufacturer Part Number
R8A77850AADBGV
Description
IC SUPERH MCU 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850AADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850AADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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18. Timer Unit (TMU)
18.4
Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR).
Each TCNT performs count-down operation. The channels have an auto-reload function that
allows cyclic count operations, and can also perform external event counting. Channel 2 also has
an input capture function.
18.4.1
When one of bits STR0 to STR2 in TSTR is set to 1, the TCNT for the corresponding channel
starts counting. When TCNT underflows, the UNF flag in TCR is set. If the UNIE bit in TCR is
set to 1 at this time, an interrupt request is sent to the CPU. At the same time, the value is copied
from TCOR into TCNT, and the count-down continues (auto-reload function).
(1)
Figure 18.2 shows an example of the counter operation setting procedure.
Rev.1.00 Jan. 10, 2008 Page 810 of 1658
REJ09B0261-0100
Note:
Example of Counter Operation Setting Procedure
When an interrupt is generated, clear the source flag in the interrupt handler processing.
If the interrupt is enabled without clearing the flag, another interrupt will be generated.
Counter operation setup
Operation
Counter Operation
Load the counter with
Select counter clock
interrupt generation
Set timer constant
Set up underflow
the initial value
Start counting
register
Figure 18.2 Example of Count Operation Setting Procedure
Set up input capture
interrupt generation
(1)
(2)
(4)
(5)
(6)
input capture
When using
function
(3)
(1)
(2)
(3)
(4)
(5)
(6)
Select the counter clock with the TPSC2 to TPSC0 bits
in TCR. When the external clock (TCLK) is selected,
specify the external clock edge with the CKEG1 and
CKEG0 bits in TCR.
Specify whether an interrupt is generated on TCNT
underflow with the UNIE bit in TCR.
When the input capture function is used, set the ICPE
bits in TCR, which also specify the use of the interrupt
function.
Set a value in TCOR.
Set the initial value in TCNT.
Set the STR bit in TSTR to 1 to start counting.
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