R8A77850AADBGV Renesas Electronics America, R8A77850AADBGV Datasheet - Page 172
R8A77850AADBGV
Manufacturer Part Number
R8A77850AADBGV
Description
IC SUPERH MCU 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850AADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850AADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 172 of 1694
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6. Floating-Point Unit (FPU)
6.6
This LSI supports two kinds of graphics functions: new instructions for geometric operations, and
pair single-precision transfer instructions that enable high-speed data transfer.
6.6.1
Geometric operation instructions perform approximate-value computations. To enable high-speed
computation with a minimum of hardware, this LSI ignores comparatively small values in the
partial computation results of four multiplications. Consequently, the error shown below is
produced in the result of the computation:
Maximum error = MAX (individual multiplication result ×
The number of significant digits is 24 for a normalized number and 23 for a denormalized number
(number of leading zeros in the fractional part).
In a future version of the SH Series, the above error is guaranteed, but the same result between
different processor cores is not guaranteed.
(1)
This instruction is basically used for the following purposes:
• Inner product (m ≠ n):
• Sum of square of elements (m = n):
Since an inexact exception is not detected by an FIPR instruction, the inexact exception (I) bit in
both the FPU exception cause field and flag field are always set to 1 when an FIPR instruction is
executed. Therefore, if the I bit is set in the FPU exception enable field, FPU exception handling
will be executed.
Rev.1.00 Jan. 10, 2008 Page 140 of 1658
REJ09B0261-0100
This operation is generally used for surface/rear surface determination for polygon surfaces.
This operation is generally used to find the length of a vector.
FIPR FVm, FVn (m, n: 0, 4, 8, 12)
Graphics Support Functions
Geometric Operation Instructions
2
–MIN (number of multiplier significant digits–1, number of multiplicand significant digits–1)
) + MAX (result value × 2
–23
, 2
–149
)
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